library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps7 is
port(clk:in std_logic;
load:in std_logic;
q:out std_logic;
count1:out std_logic_vector(7 downto 0) );
end ps7;
architecture behav of ps7 is
signal c0,c1,c2,c3:std_logic;
signal count:std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
begin
if rising_edge(clk) then
  count<=count + 1;
end if;
end process;
process(count(7),load)
begin
if (load='1') then
c3<='1';
c2<='0';
c1<='0';
c0<='1';
q<=c3;
elsif  count(7) 'event and count(7)='0' then
c1<=c0;
c2<=c1;
c3<=c2;
c0<= c0 xor c3;
q<=c3;
end if;
end process;
count1<=count;
end behav;