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--F1_q[0] is fsk_decode:u7|q[0] at LC_X8_Y18_N0
--operation mode is arithmetic

F1_q[0]_lut_out = !F1_q[0];
F1_q[0] = DFFEAS(F1_q[0]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L32 is fsk_decode:u7|q[0]~106 at LC_X8_Y18_N0
--operation mode is arithmetic

F1L32_cout_0 = F1_q[0];
F1L32 = CARRY(F1L32_cout_0);

--F1L42 is fsk_decode:u7|q[0]~106COUT1_138 at LC_X8_Y18_N0
--operation mode is arithmetic

F1L42_cout_1 = F1_q[0];
F1L42 = CARRY(F1L42_cout_1);


--F1_q[1] is fsk_decode:u7|q[1] at LC_X8_Y18_N1
--operation mode is arithmetic

F1_q[1]_lut_out = F1_q[1] $ (F1L32);
F1_q[1] = DFFEAS(F1_q[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L62 is fsk_decode:u7|q[1]~110 at LC_X8_Y18_N1
--operation mode is arithmetic

F1L62_cout_0 = !F1L32 # !F1_q[1];
F1L62 = CARRY(F1L62_cout_0);

--F1L72 is fsk_decode:u7|q[1]~110COUT1_139 at LC_X8_Y18_N1
--operation mode is arithmetic

F1L72_cout_1 = !F1L42 # !F1_q[1];
F1L72 = CARRY(F1L72_cout_1);


--F1_q[2] is fsk_decode:u7|q[2] at LC_X8_Y18_N2
--operation mode is arithmetic

F1_q[2]_lut_out = F1_q[2] $ (!F1L62);
F1_q[2] = DFFEAS(F1_q[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L92 is fsk_decode:u7|q[2]~114 at LC_X8_Y18_N2
--operation mode is arithmetic

F1L92_cout_0 = F1_q[2] & (!F1L62);
F1L92 = CARRY(F1L92_cout_0);

--F1L03 is fsk_decode:u7|q[2]~114COUT1_140 at LC_X8_Y18_N2
--operation mode is arithmetic

F1L03_cout_1 = F1_q[2] & (!F1L72);
F1L03 = CARRY(F1L03_cout_1);


--F1_q[3] is fsk_decode:u7|q[3] at LC_X8_Y18_N3
--operation mode is arithmetic

F1_q[3]_lut_out = F1_q[3] $ F1L92;
F1_q[3] = DFFEAS(F1_q[3]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L23 is fsk_decode:u7|q[3]~118 at LC_X8_Y18_N3
--operation mode is arithmetic

F1L23_cout_0 = !F1L92 # !F1_q[3];
F1L23 = CARRY(F1L23_cout_0);

--F1L33 is fsk_decode:u7|q[3]~118COUT1 at LC_X8_Y18_N3
--operation mode is arithmetic

F1L33_cout_1 = !F1L03 # !F1_q[3];
F1L33 = CARRY(F1L33_cout_1);


--F1_q[4] is fsk_decode:u7|q[4] at LC_X8_Y18_N4
--operation mode is arithmetic

F1_q[4]_lut_out = F1_q[4] $ !F1L23;
F1_q[4] = DFFEAS(F1_q[4]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L53 is fsk_decode:u7|q[4]~122 at LC_X8_Y18_N4
--operation mode is arithmetic

F1L53 = F1L63;


--F1_q[5] is fsk_decode:u7|q[5] at LC_X8_Y18_N5
--operation mode is arithmetic

F1_q[5]_carry_eqn = (!F1L53 & GND) # (F1L53 & VCC);
F1_q[5]_lut_out = F1_q[5] $ F1_q[5]_carry_eqn;
F1_q[5] = DFFEAS(F1_q[5]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L93 is fsk_decode:u7|q[5]~126 at LC_X8_Y18_N5
--operation mode is arithmetic

F1L93_cout_0 = !F1L53 # !F1_q[5];
F1L93 = CARRY(F1L93_cout_0);

--F1L04 is fsk_decode:u7|q[5]~126COUT1_141 at LC_X8_Y18_N5
--operation mode is arithmetic

F1L04_cout_1 = !F1L53 # !F1_q[5];
F1L04 = CARRY(F1L04_cout_1);


--F1_q[6] is fsk_decode:u7|q[6] at LC_X8_Y18_N6
--operation mode is arithmetic

F1_q[6]_carry_eqn = (!F1L53 & F1L93) # (F1L53 & F1L04);
F1_q[6]_lut_out = F1_q[6] $ (!F1_q[6]_carry_eqn);
F1_q[6] = DFFEAS(F1_q[6]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--F1L24 is fsk_decode:u7|q[6]~130 at LC_X8_Y18_N6
--operation mode is arithmetic

F1L24_cout_0 = F1_q[6] & (!F1L93);
F1L24 = CARRY(F1L24_cout_0);

--F1L34 is fsk_decode:u7|q[6]~130COUT1_142 at LC_X8_Y18_N6
--operation mode is arithmetic

F1L34_cout_1 = F1_q[6] & (!F1L04);
F1L34 = CARRY(F1L34_cout_1);


--F1_q[7] is fsk_decode:u7|q[7] at LC_X8_Y18_N7
--operation mode is normal

F1_q[7]_carry_eqn = (!F1L53 & F1L24) # (F1L53 & F1L34);
F1_q[7]_lut_out = F1_q[7] $ (F1_q[7]_carry_eqn);
F1_q[7] = DFFEAS(F1_q[7]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--H1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[0] at M4K_X17_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 8
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[0] = H1_q_a[0]_PORT_A_data_out_reg[0];

--H1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[7] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[7] = H1_q_a[0]_PORT_A_data_out_reg[7];

--H1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[6] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[6] = H1_q_a[0]_PORT_A_data_out_reg[6];

--H1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[5] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[5] = H1_q_a[0]_PORT_A_data_out_reg[5];

--H1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[4] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[4] = H1_q_a[0]_PORT_A_data_out_reg[4];

--H1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[3] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[3] = H1_q_a[0]_PORT_A_data_out_reg[3];

--H1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[2] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[2] = H1_q_a[0]_PORT_A_data_out_reg[2];

--H1_q_a[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_5mp:auto_generated|q_a[1] at M4K_X17_Y12
H1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = GLOBAL(CLK);
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0]_PORT_A_data_out_reg = DFFE(H1_q_a[0]_PORT_A_data_out, H1_q_a[0]_clock_0, , , );
H1_q_a[1] = H1_q_a[0]_PORT_A_data_out_reg[1];


--F1_s is fsk_decode:u7|s at LC_X9_Y18_N4
--operation mode is normal

F1_s_lut_out = F1_m[4] # F1_m[2] & F1_m[3] & !F1L1;
F1_s = DFFEAS(F1_s_lut_out, !GLOBAL(F1_q[7]), VCC, , , , , , );


--C2_DOUT[0] is REG7B:u5|DOUT[0] at LC_X15_Y12_N2
--operation mode is normal

C2_DOUT[0]_lut_out = GND;
C2_DOUT[0] = DFFEAS(C2_DOUT[0]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[0], , , VCC);


--C2_DOUT[1] is REG7B:u5|DOUT[1] at LC_X14_Y12_N2
--operation mode is normal

C2_DOUT[1]_lut_out = C1_DOUT[1];
C2_DOUT[1] = DFFEAS(C2_DOUT[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--C2_DOUT[2] is REG7B:u5|DOUT[2] at LC_X14_Y11_N2
--operation mode is normal

C2_DOUT[2]_lut_out = C1_DOUT[2];
C2_DOUT[2] = DFFEAS(C2_DOUT[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--C2_DOUT[3] is REG7B:u5|DOUT[3] at LC_X13_Y12_N9
--operation mode is normal

C2_DOUT[3]_lut_out = GND;
C2_DOUT[3] = DFFEAS(C2_DOUT[3]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[3], , , VCC);


--C2_DOUT[4] is REG7B:u5|DOUT[4] at LC_X15_Y11_N2
--operation mode is normal

C2_DOUT[4]_lut_out = GND;
C2_DOUT[4] = DFFEAS(C2_DOUT[4]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[4], , , VCC);


--C2_DOUT[5] is REG7B:u5|DOUT[5] at LC_X16_Y12_N2
--operation mode is normal

C2_DOUT[5]_lut_out = GND;
C2_DOUT[5] = DFFEAS(C2_DOUT[5]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[5], , , VCC);


--C2_DOUT[6] is REG7B:u5|DOUT[6] at LC_X13_Y12_N0
--operation mode is normal

C2_DOUT[6]_lut_out = GND;
C2_DOUT[6] = DFFEAS(C2_DOUT[6]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[6], , , VCC);


--F1_m[0] is fsk_decode:u7|m[0] at LC_X9_Y18_N5
--operation mode is arithmetic

F1_m[0]_lut_out = F1L02 $ !F1_m[0];
F1_m[0] = DFFEAS(F1_m[0]_lut_out, GLOBAL(CLK), VCC, , , , , F1L3, );

--F1L6 is fsk_decode:u7|m[0]~78 at LC_X9_Y18_N5
--operation mode is arithmetic

F1L6_cout_0 = !F1L02 & F1_m[0];
F1L6 = CARRY(F1L6_cout_0);

--F1L7 is fsk_decode:u7|m[0]~78COUT1_98 at LC_X9_Y18_N5
--operation mode is arithmetic

F1L7_cout_1 = !F1L02 & F1_m[0];
F1L7 = CARRY(F1L7_cout_1);


--F1_m[1] is fsk_decode:u7|m[1] at LC_X9_Y18_N6
--operation mode is arithmetic

F1_m[1]_lut_out = F1_m[1] $ (F1L6);
F1_m[1] = DFFEAS(F1_m[1]_lut_out, GLOBAL(CLK), VCC, , , , , F1L3, );

--F1L9 is fsk_decode:u7|m[1]~82 at LC_X9_Y18_N6
--operation mode is arithmetic

F1L9_cout_0 = !F1L6 # !F1_m[1];
F1L9 = CARRY(F1L9_cout_0);

--F1L01 is fsk_decode:u7|m[1]~82COUT1 at LC_X9_Y18_N6
--operation mode is arithmetic

F1L01_cout_1 = !F1L7 # !F1_m[1];
F1L01 = CARRY(F1L01_cout_1);


--F1L1 is fsk_decode:u7|LessThan~313 at LC_X9_Y18_N1
--operation mode is normal

F1L1 = !F1_m[0] & (!F1_m[1]);


--F1_m[2] is fsk_decode:u7|m[2] at LC_X9_Y18_N7
--operation mode is arithmetic

F1_m[2]_lut_out = F1_m[2] $ (!F1L9);
F1_m[2] = DFFEAS(F1_m[2]_lut_out, GLOBAL(CLK), VCC, , , , , F1L3, );

--F1L21 is fsk_decode:u7|m[2]~86 at LC_X9_Y18_N7
--operation mode is arithmetic

F1L21_cout_0 = F1_m[2] & (!F1L9);
F1L21 = CARRY(F1L21_cout_0);

--F1L31 is fsk_decode:u7|m[2]~86COUT1_99 at LC_X9_Y18_N7
--operation mode is arithmetic

F1L31_cout_1 = F1_m[2] & (!F1L01);
F1L31 = CARRY(F1L31_cout_1);


--F1_m[3] is fsk_decode:u7|m[3] at LC_X9_Y18_N8
--operation mode is arithmetic

F1_m[3]_lut_out = F1_m[3] $ F1L21;
F1_m[3] = DFFEAS(F1_m[3]_lut_out, GLOBAL(CLK), VCC, , , , , F1L3, );

--F1L51 is fsk_decode:u7|m[3]~90 at LC_X9_Y18_N8
--operation mode is arithmetic

F1L51_cout_0 = !F1L21 # !F1_m[3];
F1L51 = CARRY(F1L51_cout_0);

--F1L61 is fsk_decode:u7|m[3]~90COUT1_100 at LC_X9_Y18_N8
--operation mode is arithmetic

F1L61_cout_1 = !F1L31 # !F1_m[3];
F1L61 = CARRY(F1L61_cout_1);


--F1_m[4] is fsk_decode:u7|m[4] at LC_X9_Y18_N9
--operation mode is normal

F1_m[4]_lut_out = F1_m[4] $ (!F1L51);
F1_m[4] = DFFEAS(F1_m[4]_lut_out, GLOBAL(CLK), VCC, , , , , F1L3, );