library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsk_decode IS                                     --解調程序
    PORT (     CLK : IN  STD_LOGIC;
            receive  : in STD_LOGIC_VECTOR(7 DOWNTO 0) ;
             s:out std_logic);
 END;
architecture behave of  fsk_decode is
signal q:std_logic_vector(7 downto 0):=(others=>'0');
signal m:STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";    --過零檢測的計數器
signal reg:STD_LOGIC_VECTOR(7 DOWNTO 0);           --暫存接收到的dds信號
begin
 process(clk)
   begin
if clk 'event and clk='1' then
   q<=q+1;reg<=receive;
end if;
 end process;
process(q(7))
begin 
if q(7) 'event and q(7)='0' then
    if m<13 then  s<='0';   --根據判斷的次數，解調出信號
     else  s<='1';
   end if; 
end if;
end process;
process(clk)       
   begin
if clk 'event and clk='1' then
    if q<"00000010" then m<="00000";
    elsif reg>"01111000" and reg<"10001000" then m<=m+1;
                --對接收到的信號，檢測通過一定范圍的次數
    end if;   
end if;
end process;
end behave;