/********************************************************************************    File Name:  rcvr.v*      Version:  1.1*         Date:  January 22, 2000*        Model:  Receiver Chip**      Company:  Xilinx***   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.**                Copyright (c) 2000 Xilinx, Inc.*                All rights reserved*******************************************************************************/`timescale 1 ns / 1 nsmodule rcvr (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ;input rxd ;input clk16x ;input rst ;input rdn ;output [7:0] dout ;output data_ready ;output framing_error ;output parity_error ;reg rxd1 ;reg rxd2 ;reg clk1x_enable ;reg [3:0] clkdiv ;reg [7:0] rsr ;reg [7:0] rbr ;reg [3:0] no_bits_rcvd ;reg data_ready ;reg parity ;reg parity_error ;reg framing_error ;wire clk1x ;assign dout = !rdn ? rbr : 8'bz ;always @(posedge clk16x or negedge rst)beginif (!rst)beginrxd1 <= 1'b1 ;rxd2 <= 1'b1 ;endelse beginrxd1 <= rxd ;rxd2 <= rxd1 ;endendalways @(posedge clk16x or negedge rst)beginif (!rst)clk1x_enable <= 1'b0;else if (!rxd1 && rxd2)clk1x_enable <= 1'b1 ;else if (no_bits_rcvd == 4'b1100)clk1x_enable <= 1'b0 ;endalways @(posedge clk16x or negedge rst or negedge rdn)beginif (!rst)data_ready = 1'b0 ;else if (!rdn)data_ready = 1'b0 ;elseif (no_bits_rcvd == 4'b1011)data_ready = 1'b1 ;endalways @(posedge clk16x or negedge rst)beginif (!rst)clkdiv = 4'b0000 ;else if (clk1x_enable)clkdiv = clkdiv +1 ;endassign clk1x = clkdiv[3] ;always @(posedge clk1x or negedge rst)if (!rst)beginrsr <= 8'b0 ;rbr <= 8'b0 ;parity <= 1'b1 ;framing_error = 1'b0 ;parity_error = 1'b0 ;endelse beginif (no_bits_rcvd >= 4'b0001 && no_bits_rcvd <= 4'b1001) beginrsr[0] <= rxd2 ;rsr[7:1] <= rsr[6:0] ;parity <= parity ^ rsr[7] ;endelse if (no_bits_rcvd == 4'b1010)beginrbr <= rsr ;endelse if (!parity) parity_error = 1'b1 ;else if ((no_bits_rcvd == 4'b1011) && (rxd2 != 1'b1))framing_error = 1'b1 ;elseframing_error = 1'b0 ;endalways @(posedge clk1x or negedge rst or negedge clk1x_enable)if (!rst)no_bits_rcvd = 4'b0000;elseif (!clk1x_enable)no_bits_rcvd = 4'b0000 ;elseno_bits_rcvd = no_bits_rcvd + 1 ;endmodule