# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ps2rs232_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C8
set_global_assignment -name TOP_LEVEL_ENTITY ps2rs232
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:40  OCTOBER 07, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_FILE txmit.v
set_global_assignment -name VERILOG_FILE rcvr.v
set_global_assignment -name VERILOG_FILE div_4.v
set_global_assignment -name VERILOG_FILE ps2_keyboard_interface.v
set_global_assignment -name BDF_FILE ps2rs232.bdf
set_global_assignment -name VERILOG_FILE uart_if.v
set_global_assignment -name VERILOG_FILE div_256.v
set_global_assignment -name VERILOG_FILE data_buf.v
set_global_assignment -name VERILOG_FILE uart.v
set_location_assignment PIN_E22 -to ps2_clk
set_location_assignment PIN_E21 -to ps2_data
set_location_assignment PIN_AA3 -to rst
set_location_assignment PIN_B14 -to txd
set_location_assignment PIN_A20 -to rx_ascii[0]
set_location_assignment PIN_A17 -to rx_ascii[1]
set_location_assignment PIN_A15 -to rx_ascii[2]
set_location_assignment PIN_A11 -to rx_ascii[3]
set_location_assignment PIN_B10 -to rx_ascii[4]
set_location_assignment PIN_B8 -to rx_ascii[5]
set_location_assignment PIN_A5 -to rx_ascii[6]
set_location_assignment PIN_B3 -to rx_ascii[7]
set_location_assignment PIN_W12 -to mclk