|ps2rs232
tx_write_ack_o <= ps2_keyboard_interface:inst1.tx_write_ack_o
mclk => div_256:inst4.mclk
mclk => div_4:inst.clk50m
rst => div_256:inst4.reset
rst => ps2_keyboard_interface:inst1.reset
rx_read => ps2_keyboard_interface:inst1.rx_read
ps2_clk <= ps2_keyboard_interface:inst1.ps2_clk
ps2_data <= ps2_keyboard_interface:inst1.ps2_data
txd <= uart_if:inst3.txd
rx_ascii[0] <= ps2_keyboard_interface:inst1.rx_ascii[0]
rx_ascii[1] <= ps2_keyboard_interface:inst1.rx_ascii[1]
rx_ascii[2] <= ps2_keyboard_interface:inst1.rx_ascii[2]
rx_ascii[3] <= ps2_keyboard_interface:inst1.rx_ascii[3]
rx_ascii[4] <= ps2_keyboard_interface:inst1.rx_ascii[4]
rx_ascii[5] <= ps2_keyboard_interface:inst1.rx_ascii[5]
rx_ascii[6] <= ps2_keyboard_interface:inst1.rx_ascii[6]
rx_ascii[7] <= ps2_keyboard_interface:inst1.rx_ascii[7]


|ps2rs232|ps2_keyboard_interface:inst1
clk => ps2_data_s.CLK
clk => m2_state.CLK
clk => bit_count[3].CLK
clk => bit_count[2].CLK
clk => bit_count[1].CLK
clk => bit_count[0].CLK
clk => q[10].CLK
clk => q[9].CLK
clk => q[8].CLK
clk => q[7].CLK
clk => q[6].CLK
clk => q[5].CLK
clk => q[4].CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => timer_60usec_count[11].CLK
clk => timer_60usec_count[10].CLK
clk => timer_60usec_count[9].CLK
clk => timer_60usec_count[8].CLK
clk => timer_60usec_count[7].CLK
clk => timer_60usec_count[6].CLK
clk => timer_60usec_count[5].CLK
clk => timer_60usec_count[4].CLK
clk => timer_60usec_count[3].CLK
clk => timer_60usec_count[2].CLK
clk => timer_60usec_count[1].CLK
clk => timer_60usec_count[0].CLK
clk => timer_5usec_count[7].CLK
clk => timer_5usec_count[6].CLK
clk => timer_5usec_count[5].CLK
clk => timer_5usec_count[4].CLK
clk => timer_5usec_count[3].CLK
clk => timer_5usec_count[2].CLK
clk => timer_5usec_count[1].CLK
clk => timer_5usec_count[0].CLK
clk => hold_extended.CLK
clk => hold_released.CLK
clk => left_shift_key.CLK
clk => right_shift_key.CLK
clk => rx_extended~reg0.CLK
clk => rx_released~reg0.CLK
clk => rx_scan_code[7]~reg0.CLK
clk => rx_scan_code[6]~reg0.CLK
clk => rx_scan_code[5]~reg0.CLK
clk => rx_scan_code[4]~reg0.CLK
clk => rx_scan_code[3]~reg0.CLK
clk => rx_scan_code[2]~reg0.CLK
clk => rx_scan_code[1]~reg0.CLK
clk => rx_scan_code[0]~reg0.CLK
clk => rx_ascii[7]~reg0.CLK
clk => rx_ascii[6]~reg0.CLK
clk => rx_ascii[5]~reg0.CLK
clk => rx_ascii[4]~reg0.CLK
clk => rx_ascii[3]~reg0.CLK
clk => rx_ascii[2]~reg0.CLK
clk => rx_ascii[1]~reg0.CLK
clk => rx_ascii[0]~reg0.CLK
clk => ps2_clk_s.CLK
clk => m1_state~15.IN1
reset => m2_state~0.OUTPUTSELECT
reset => left_shift_key~2.OUTPUTSELECT
reset => right_shift_key~2.OUTPUTSELECT
reset => rx_extended~1.OUTPUTSELECT
reset => rx_released~1.OUTPUTSELECT
reset => rx_scan_code~8.OUTPUTSELECT
reset => rx_scan_code~9.OUTPUTSELECT
reset => rx_scan_code~10.OUTPUTSELECT
reset => rx_scan_code~11.OUTPUTSELECT
reset => rx_scan_code~12.OUTPUTSELECT
reset => rx_scan_code~13.OUTPUTSELECT
reset => rx_scan_code~14.OUTPUTSELECT
reset => rx_scan_code~15.OUTPUTSELECT
reset => rx_ascii~8.OUTPUTSELECT
reset => rx_ascii~9.OUTPUTSELECT
reset => rx_ascii~10.OUTPUTSELECT
reset => rx_ascii~11.OUTPUTSELECT
reset => rx_ascii~12.OUTPUTSELECT
reset => rx_ascii~13.OUTPUTSELECT
reset => rx_ascii~14.OUTPUTSELECT
reset => rx_ascii~15.OUTPUTSELECT
reset => m1_state~0.OUTPUTSELECT
reset => m1_state~1.OUTPUTSELECT
reset => m1_state~2.OUTPUTSELECT
reset => m1_state~3.OUTPUTSELECT
reset => m1_state~4.OUTPUTSELECT
reset => m1_state~5.OUTPUTSELECT
reset => m1_state~6.OUTPUTSELECT
reset => m1_state~7.OUTPUTSELECT
reset => m1_state~8.OUTPUTSELECT
reset => m1_state~9.OUTPUTSELECT
reset => m1_state~10.OUTPUTSELECT
reset => m1_state~11.OUTPUTSELECT
reset => m1_state~12.OUTPUTSELECT
reset => m1_state~13.OUTPUTSELECT
reset => m1_state~14.OUTPUTSELECT
reset => always5~0.IN1
reset => q~22.OUTPUTSELECT
reset => q~23.OUTPUTSELECT
reset => q~24.OUTPUTSELECT
reset => q~25.OUTPUTSELECT
reset => q~26.OUTPUTSELECT
reset => q~27.OUTPUTSELECT
reset => q~28.OUTPUTSELECT
reset => q~29.OUTPUTSELECT
reset => q~30.OUTPUTSELECT
reset => q~31.OUTPUTSELECT
reset => q~32.OUTPUTSELECT
reset => always9~0.IN0
ps2_clk <= ps2_clk~0
ps2_data <= ps2_data~0
rx_extended <= rx_extended~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_released <= rx_released~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_shift_key_on <= rx_shift_key_on~0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[0] <= rx_scan_code[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[1] <= rx_scan_code[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[2] <= rx_scan_code[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[3] <= rx_scan_code[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[4] <= rx_scan_code[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[5] <= rx_scan_code[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[6] <= rx_scan_code[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_scan_code[7] <= rx_scan_code[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[0] <= rx_ascii[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[1] <= rx_ascii[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[2] <= rx_ascii[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[3] <= rx_ascii[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[4] <= rx_ascii[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[5] <= rx_ascii[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[6] <= rx_ascii[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ascii[7] <= rx_ascii[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_ready <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
rx_read => m2_next_state.DATAB
tx_data[0] => WideXnor0.IN7
tx_data[0] => q~20.DATAB
tx_data[1] => WideXnor0.IN6
tx_data[1] => q~19.DATAB
tx_data[2] => WideXnor0.IN5
tx_data[2] => q~18.DATAB
tx_data[3] => WideXnor0.IN4
tx_data[3] => q~17.DATAB
tx_data[4] => WideXnor0.IN3
tx_data[4] => q~16.DATAB
tx_data[5] => WideXnor0.IN2
tx_data[5] => q~15.DATAB
tx_data[6] => WideXnor0.IN1
tx_data[6] => q~14.DATAB
tx_data[7] => WideXnor0.IN0
tx_data[7] => q~13.DATAB
tx_write => m1_next_state~0.OUTPUTSELECT
tx_write => m1_next_state~1.OUTPUTSELECT
tx_write => Selector10.IN2
tx_write => tx_write_ack_o~0.IN1
tx_write => tx_write_ack_o~1.IN1
tx_write_ack_o <= tx_write_ack_o~2.DB_MAX_OUTPUT_PORT_TYPE
tx_error_no_keyboard_ack <= m1_state.m1_tx_error_no_keyboard_ack.DB_MAX_OUTPUT_PORT_TYPE


|ps2rs232|div_256:inst4
mclk => count[5].CLK
mclk => count[4].CLK
mclk => count[3].CLK
mclk => count[2].CLK
mclk => count[1].CLK
mclk => count[0].CLK
mclk => clk~reg0.CLK
mclk => count[6].CLK
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[6].ACLR
reset => clk~reg0.ENA
clk <= clk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ps2rs232|uart_if:inst3
clk => clk~0.IN1
rst_n => rst.IN1
rst_n => data_out[6]~reg0.ACLR
rst_n => data_out[5]~reg0.ACLR
rst_n => data_out[4]~reg0.ACLR
rst_n => data_out[3]~reg0.ACLR
rst_n => data_out[2]~reg0.ACLR
rst_n => data_out[1]~reg0.ACLR
rst_n => data_out[0]~reg0.ACLR
rst_n => data_out_d[7].ACLR
rst_n => data_out_d[6].ACLR
rst_n => data_out_d[5].ACLR
rst_n => data_out_d[4].ACLR
rst_n => data_out_d[3].ACLR
rst_n => data_out_d[2].ACLR
rst_n => data_out_d[1].ACLR
rst_n => data_out_d[0].ACLR
rst_n => din[7].ACLR
rst_n => din[6].ACLR
rst_n => din[5].ACLR
rst_n => din[4].ACLR
rst_n => din[3].ACLR
rst_n => din[2].ACLR
rst_n => din[1].ACLR
rst_n => din[0].ACLR
rst_n => wrn.PRESET
rst_n => cnt[2].ACLR
rst_n => data_out[7]~reg0.ACLR
rst_n => cnt[1].ACLR
rst_n => cnt[0].ACLR
rst_n => cnt[3].ACLR
rst_n => rdn_d2.PRESET
rst_n => rdn.PRESET
rst_n => rdn_d.PRESET
rst_n => read_en.PRESET
rst_n => read_once.ENA
txd <= uart:U1.sdo
rxd => rxd~0.IN1
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[0] => din~15.DATAB
data_in[1] => din~14.DATAB
data_in[2] => din~13.DATAB
data_in[3] => din~12.DATAB
data_in[4] => din~11.DATAB
data_in[5] => din~10.DATAB
data_in[6] => din~9.DATAB
data_in[7] => din~8.DATAB


|ps2rs232|uart_if:inst3|uart:U1
dout[0] <= rcvr:u1.port0
dout[1] <= rcvr:u1.port0
dout[2] <= rcvr:u1.port0
dout[3] <= rcvr:u1.port0
dout[4] <= rcvr:u1.port0
dout[5] <= rcvr:u1.port0
dout[6] <= rcvr:u1.port0
dout[7] <= rcvr:u1.port0
data_ready <= rcvr:u1.port1
framing_error <= rcvr:u1.port2
parity_error <= rcvr:u1.port3
rxd => rxd~0.IN1
clk16x => clk16x~0.IN2
rst => rst~0.IN2
rdn => rdn~0.IN1
din[0] => din[0]~7.IN1
din[1] => din[1]~6.IN1
din[2] => din[2]~5.IN1
din[3] => din[3]~4.IN1
din[4] => din[4]~3.IN1
din[5] => din[5]~2.IN1
din[6] => din[6]~1.IN1
din[7] => din[7]~0.IN1
tbre <= txmit:u2.port1
tsre <= txmit:u2.port2
wrn => wrn~0.IN1
sdo <= txmit:u2.port6


|ps2rs232|uart_if:inst3|uart:U1|rcvr:u1
dout[0] <= dout~7.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout~6.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout~5.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout~4.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout~3.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout~1.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout~0.DB_MAX_OUTPUT_PORT_TYPE
data_ready <= data_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
rxd => rxd1.DATAIN
clk16x => rxd2.CLK
clk16x => clk1x_enable.CLK
clk16x => data_ready~reg0.CLK
clk16x => clkdiv[3].CLK
clk16x => clkdiv[2].CLK
clk16x => clkdiv[1].CLK
clk16x => clkdiv[0].CLK
clk16x => rxd1.CLK
rst => rsr[6].ACLR
rst => rsr[5].ACLR
rst => rsr[4].ACLR
rst => rsr[3].ACLR
rst => rsr[2].ACLR
rst => rsr[1].ACLR
rst => rsr[0].ACLR
rst => rbr[7].ACLR
rst => rbr[6].ACLR
rst => rbr[5].ACLR
rst => rbr[4].ACLR
rst => rbr[3].ACLR
rst => rbr[2].ACLR
rst => rbr[1].ACLR
rst => rbr[0].ACLR
rst => parity.PRESET
rst => framing_error~reg0.ACLR
rst => parity_error~reg0.ACLR
rst => data_ready~0.IN0
rst => rsr[7].ACLR
rst => clk1x_enable.ACLR
rst => clkdiv[2].ACLR
rst => clkdiv[1].ACLR
rst => clkdiv[0].ACLR
rst => clkdiv[3].ACLR
rst => no_bits_rcvd~0.IN1
rst => rxd1.PRESET
rst => rxd2.PRESET
rdn => data_ready~0.IN1
rdn => dout~0.OE
rdn => dout~1.OE
rdn => dout~2.OE
rdn => dout~3.OE
rdn => dout~4.OE
rdn => dout~5.OE
rdn => dout~6.OE
rdn => dout~7.OE


|ps2rs232|uart_if:inst3|uart:U1|txmit:u2
din[0] => tbr[0].DATAIN
din[1] => tbr[1].DATAIN
din[2] => tbr[2].DATAIN
din[3] => tbr[3].DATAIN
din[4] => tbr[4].DATAIN
din[5] => tbr[5].DATAIN
din[6] => tbr[6].DATAIN
din[7] => tbr[7].DATAIN
tbre <= tbre~reg0.DB_MAX_OUTPUT_PORT_TYPE
tsre <= tsre~reg0.DB_MAX_OUTPUT_PORT_TYPE
rst => wrn2.PRESET
rst => tbre~reg0.ACLR
rst => clk1x_enable.ACLR
rst => tbr[7].ACLR
rst => tbr[6].ACLR
rst => tbr[5].ACLR
rst => tbr[4].ACLR
rst => tbr[3].ACLR
rst => tbr[2].ACLR
rst => tbr[1].ACLR
rst => tbr[0].ACLR
rst => clkdiv[3].ACLR
rst => clkdiv[2].ACLR
rst => clkdiv[1].ACLR
rst => clkdiv[0].ACLR
rst => sdo~reg0.PRESET
rst => tsre~reg0.PRESET
rst => parity.PRESET
rst => tsr[7].ACLR
rst => tsr[6].ACLR
rst => tsr[5].ACLR
rst => tsr[4].ACLR
rst => tsr[3].ACLR
rst => tsr[2].ACLR
rst => tsr[1].ACLR
rst => tsr[0].ACLR
rst => no_bits_sent~0.IN1
rst => wrn1.PRESET
clk16x => wrn2.CLK
clk16x => tbre~reg0.CLK
clk16x => clk1x_enable.CLK
clk16x => clkdiv[3].CLK
clk16x => clkdiv[2].CLK
clk16x => clkdiv[1].CLK
clk16x => clkdiv[0].CLK
clk16x => wrn1.CLK
wrn => wrn1.DATAIN
wrn => tbr[6].CLK
wrn => tbr[5].CLK
wrn => tbr[4].CLK
wrn => tbr[3].CLK
wrn => tbr[2].CLK
wrn => tbr[1].CLK
wrn => tbr[0].CLK
wrn => tbr[7].CLK
sdo <= sdo~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ps2rs232|div_4:inst
clk50m => acc[11].CLK
clk50m => acc[10].CLK
clk50m => acc[9].CLK
clk50m => acc[8].CLK
clk50m => acc[7].CLK
clk50m => acc[6].CLK
clk50m => acc[5].CLK
clk50m => acc[4].CLK
clk50m => acc[3].CLK
clk50m => acc[2].CLK
clk50m => acc[1].CLK
clk50m => acc[0].CLK
clk50m => acc[12].CLK
clk1_8m <= acc[12].DB_MAX_OUTPUT_PORT_TYPE


|ps2rs232|data_buf:inst5
data_in[0] => comb~6.IN1
data_in[0] => comb~15.IN1
data_in[1] => comb~5.IN1
data_in[1] => comb~14.IN1
data_in[2] => comb~4.IN1
data_in[2] => comb~13.IN1
data_in[3] => comb~3.IN1
data_in[3] => comb~12.IN1
data_in[4] => comb~2.IN1
data_in[4] => comb~11.IN1
data_in[5] => comb~1.IN1
data_in[5] => comb~10.IN1
data_in[6] => comb~0.IN1
data_in[6] => comb~9.IN1
data_in[7] => comb~7.IN1
data_in[7] => comb~8.IN1
data_in_buf[0] <= always0~8.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[1] <= always0~7.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[2] <= always0~6.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[3] <= always0~5.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[4] <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[5] <= always0~3.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[6] <= always0~2.DB_MAX_OUTPUT_PORT_TYPE
data_in_buf[7] <= always0~1.DB_MAX_OUTPUT_PORT_TYPE
clk1_8m => data_in_buf[6]~reg0.CLK
clk1_8m => data_in_buf[5]~reg0.CLK
clk1_8m => data_in_buf[4]~reg0.CLK
clk1_8m => data_in_buf[3]~reg0.CLK
clk1_8m => data_in_buf[2]~reg0.CLK
clk1_8m => data_in_buf[1]~reg0.CLK
clk1_8m => data_in_buf[0]~reg0.CLK
clk1_8m => i[3].CLK
clk1_8m => i[2].CLK
clk1_8m => i[1].CLK
clk1_8m => i[0].CLK
clk1_8m => always0~9.CLK
clk1_8m => always0~10.CLK
clk1_8m => always0~11.CLK
clk1_8m => always0~12.CLK
clk1_8m => always0~13.CLK
clk1_8m => always0~14.CLK
clk1_8m => always0~15.CLK
clk1_8m => always0~16.CLK
clk1_8m => data_in_buf[7]~reg0.CLK
reset => comb~0.IN0
reset => comb~1.IN0
reset => comb~2.IN0
reset => comb~3.IN0
reset => comb~4.IN0
reset => comb~5.IN0
reset => comb~6.IN0
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => always0~9.PRESET
reset => always0~10.PRESET
reset => always0~11.PRESET
reset => always0~12.PRESET
reset => always0~13.PRESET
reset => always0~14.PRESET
reset => always0~15.PRESET
reset => always0~16.PRESET
reset => comb~7.IN0
reset => comb~8.IN0
reset => comb~9.IN0
reset => comb~10.IN0
reset => comb~11.IN0
reset => comb~12.IN0
reset => comb~13.IN0
reset => comb~14.IN0
reset => comb~15.IN0