?? ps2rs232.tan.rpt
字號:
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F484C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; mclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'mclk' ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 103.89 MHz ( period = 9.626 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[0] ; uart_if:inst3|uart:U1|txmit:u2|tsr[0] ; mclk ; mclk ; None ; None ; 0.751 ns ;
; N/A ; 103.89 MHz ( period = 9.626 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[4] ; uart_if:inst3|uart:U1|txmit:u2|tsr[4] ; mclk ; mclk ; None ; None ; 0.751 ns ;
; N/A ; 103.93 MHz ( period = 9.622 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[2] ; uart_if:inst3|uart:U1|txmit:u2|tsr[2] ; mclk ; mclk ; None ; None ; 0.749 ns ;
; N/A ; 103.95 MHz ( period = 9.620 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[1] ; uart_if:inst3|uart:U1|txmit:u2|tsr[1] ; mclk ; mclk ; None ; None ; 0.748 ns ;
; N/A ; 103.95 MHz ( period = 9.620 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[3] ; uart_if:inst3|uart:U1|txmit:u2|tsr[3] ; mclk ; mclk ; None ; None ; 0.748 ns ;
; N/A ; 104.01 MHz ( period = 9.614 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[6] ; uart_if:inst3|uart:U1|txmit:u2|tsr[6] ; mclk ; mclk ; None ; None ; 0.745 ns ;
; N/A ; 104.10 MHz ( period = 9.606 ns ) ; uart_if:inst3|uart:U1|txmit:u2|tbr[5] ; uart_if:inst3|uart:U1|txmit:u2|tsr[5] ; mclk ; mclk ; None ; None ; 0.741 ns ;
; N/A ; 108.34 MHz ( period = 9.230 ns ) ; ps2_keyboard_interface:inst1|q[7] ; ps2_keyboard_interface:inst1|rx_ascii[1] ; mclk ; mclk ; None ; None ; 8.973 ns ;
; N/A ; 108.34 MHz ( period = 9.230 ns ) ; ps2_keyboard_interface:inst1|q[7] ; ps2_keyboard_interface:inst1|rx_ascii[6] ; mclk ; mclk ; None ; None ; 8.973 ns ;
; N/A ; 108.92 MHz ( period = 9.181 ns ) ; ps2_keyboard_interface:inst1|q[6] ; ps2_keyboard_interface:inst1|rx_ascii[1] ; mclk ; mclk ; None ; None ; 8.924 ns ;
; N/A ; 108.92 MHz ( period = 9.181 ns ) ; ps2_keyboard_interface:inst1|q[6] ; ps2_keyboard_interface:inst1|rx_ascii[6] ; mclk ; mclk ; None ; None ; 8.924 ns ;
; N/A ; 109.69 MHz ( period = 9.117 ns ) ; ps2_keyboard_interface:inst1|q[5] ; ps2_keyboard_interface:inst1|rx_ascii[1] ; mclk ; mclk ; None ; None ; 8.856 ns ;
; N/A ; 109.69 MHz ( period = 9.117 ns ) ; ps2_keyboard_interface:inst1|q[5] ; ps2_keyboard_interface:inst1|rx_ascii[6] ; mclk ; mclk ; None ; None ; 8.856 ns ;
; N/A ; 110.61 MHz ( period = 9.041 ns ) ; ps2_keyboard_interface:inst1|q[8] ; ps2_keyboard_interface:inst1|rx_ascii[1] ; mclk ; mclk ; None ; None ; 8.784 ns ;
; N/A ; 110.61 MHz ( period = 9.041 ns ) ; ps2_keyboard_interface:inst1|q[8] ; ps2_keyboard_interface:inst1|rx_ascii[6] ; mclk ; mclk ; None ; None ; 8.784 ns ;
; N/A ; 110.69 MHz ( period = 9.034 ns ) ; ps2_keyboard_interface:inst1|q[3] ; ps2_keyboard_interface:inst1|rx_ascii[1] ; mclk ; mclk ; None ; None ; 8.773 ns ;
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