8位數碼掃描顯示電路設計（VHDL）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN_LED IS                                    
    PORT (   CLK   : IN STD_LOGIC; 
              SG   : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);  --段控制信號輸出
              BT   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信號輸出
 END;
ARCHITECTURE one OF SCAN_LED IS
    SIGNAL CNT8  : STD_LOGIC_VECTOR(2 DOWNTO 0); 
    SIGNAL    A  : INTEGER RANGE 0 TO 15;
BEGIN
P1: PROCESS( CNT8 )
    BEGIN
        CASE  CNT8 IS
          WHEN "000" =>  BT <= "00000001" ; A <= 1 ;
          WHEN "001" =>  BT <= "00000010" ; A <= 3 ; 
          WHEN "010" =>  BT <= "00000100" ; A <= 5 ;
          WHEN "011" =>  BT <= "00001000" ; A <= 7 ;
          WHEN "100" =>  BT <= "00010000" ; A <= 9 ;
          WHEN "101" =>  BT <= "00100000" ; A <= 11 ;
          WHEN "110" =>  BT <= "01000000" ; A <= 13 ;
          WHEN "111" =>  BT <= "10000000" ; A <= 15 ;
          WHEN OTHERS =>  NULL ;
        END CASE ;
     END PROCESS P1;
    P2: PROCESS(CLK)
        BEGIN
         IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;   
         END IF;
    END PROCESS P2 ;   
     P3: PROCESS( A ) --譯碼電路
      BEGIN
       CASE  A  IS
        WHEN 0  => SG <= "0111111";  WHEN 1  => SG <= "0000110"; 
        WHEN 2  => SG <= "1011011";  WHEN 3  => SG <= "1001111"; 
        WHEN 4  => SG <= "1100110";  WHEN 5  => SG <= "1101101"; 
        WHEN 6  => SG <= "1111101";  WHEN 7  => SG <= "0000111";
        WHEN 8  => SG <= "1111111";  WHEN 9  => SG <= "1101111"; 
        WHEN 10 => SG <= "1110111";  WHEN 11 => SG <= "1111100";
        WHEN 12 => SG <= "0111001";  WHEN 13 => SG <= "1011110"; 
        WHEN 14 => SG <= "1111001";  WHEN 15 => SG <= "1110001";
        WHEN OTHERS =>  NULL ;
       END CASE ;
      END PROCESS P3;    
END;




2\
------------------------------------------------------------------------------------
-- DESCRIPTION   :   BIN to seven segments converter
--                   segment encoding
--                        a
--                      +---+ 
--                    f |   | b
--                      +---+  <- g
--                    e |   | c
--                      +---+
--                        d
--                  Enable (EN) active                : high
--                  Outputs (data_out) active         : low
-- Download from :  http://www.pld.com.cn
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity SEVEN_SEGMENT is
	port (
		data_in : in std_logic_vector (3 downto 0);
		EN : in std_logic;
		data_out : out std_logic_vector (6 downto 0)
	);
end entity;



architecture SEVEN_SEGMENT_arch of bin27seg is
begin

	process(data_in, EN)
	begin
		data_out <= (others => '1');
		if EN='1' then
			case data_in is
				when "0000" => data_out <= "1000000"; -- 0
				when "0001" => data_out <= "1111001"; -- 1
				when "0010" => data_out <= "0100100"; -- 2
				when "0011" => data_out <= "0110000"; -- 3
				when "0100" => data_out <= "0011001"; -- 4
				when "0101" => data_out <= "0010010"; -- 5
				when "0110" => data_out <= "0000011"; -- 6
				when "0111" => data_out <= "1111000"; -- 7
				when "1000" => data_out <= "0000000"; -- 8
				when "1001" => data_out <= "0011000"; -- 9
				when "1010" => data_out <= "0001000"; -- A
				when "1011" => data_out <= "0000011"; -- b
				when "1100" => data_out <= "0100111"; -- c
				when "1101" => data_out <= "0100001"; -- d
				when "1110" => data_out <= "0000110"; -- E
				when "1111" => data_out <= "0001110"; -- F
				when others => NULL;
			end case;
		end if;
	end process;

end architecture;

修改后
library IEEE;
use IEEE.std_logic_1164.all;

entity SEVEN_SEGMENT is
	port (
		data_in : in std_logic_vector (3 downto 0);
		EN : in std_logic;
		data_out : out std_logic_vector (6 downto 0)
	);
end entity;



architecture SEVEN_SEGMENT_arch of SEVEN_SEGMENT is
begin

	process(data_in, EN)
	begin
		data_out <= (others => '1');
		if EN='1' then
			case data_in is
				when "0000" => data_out <= "1000000"; -- 0
				when "0001" => data_out <= "1111001"; -- 1
				when "0010" => data_out <= "0100100"; -- 2
				when "0011" => data_out <= "0110000"; -- 3
				when "0100" => data_out <= "0011001"; -- 4
				when "0101" => data_out <= "0010010"; -- 5
				when "0110" => data_out <= "0000011"; -- 6
				when "0111" => data_out <= "1111000"; -- 7
				when "1000" => data_out <= "0000000"; -- 8
				when "1001" => data_out <= "0011000"; -- 9
                                when others => NULL;
                    end case;
		end if;
	end process;

end architecture;