module qep(   rst,ina,inb,clkin,clkout,dirout						);input rst,ina,inb;//復們信號，光電編碼器A相和B輸入信號input clkin;//處理時鐘輸入信號output clkout,dirout;//輸出時鐘和方向信號reg dirout;reg ina1,ina2;always @(negedge rst or posedge clkin)begin	if(!rst)begin		ina1 <= 1'b0;		ina2 <= 1'b0;	end	else begin		ina1 <= ina;		ina2 <= ina1;	endendwire ina_edge = ina1 ^ ina2;reg inb1,inb2;always @(negedge rst or posedge clkin)begin	if(!rst)begin		inb1 <= 1'b0;		inb2 <= 1'b0;	end	else begin		inb1 <= inb;		inb2 <= inb1;	endendwire inb_edge = inb1 ^ inb2;reg inb_new;wire ab = ina ^ inb;always @(negedge rst or negedge ina_edge)begin	if(!rst)begin		inb_new <= 1'b0;		dirout <= 1'b0;   end	else begin		inb_new <= inb;		dirout <= ab;	endendreg ina_new;always @(negedge rst or negedge inb_edge)begin	if(!rst)		ina_new <= 1'b0;	else		ina_new <= ina;endwire clk_temp1 = ina_new ^ inb_new;reg clk_temp2;always @(negedge rst or posedge clkin)begin	if(!rst)begin		clk_temp2 <= 1'b0;	end	else begin		clk_temp2 <= clk_temp1;	endendassign clkout = clk_temp1 ^ clk_temp2;endmodule