library ieee;
use ieee.std_logic_1164.all;
entity geweidecord is
     port(key0:in std_logic;
          key1:in std_logic;
          key2:in std_logic;
          key3:in std_logic;
          key4:in std_logic;
          key5:in std_logic;
          key6:in std_logic;
          key7:in std_logic;
          key8:in std_logic;
          key9:in std_logic;
          bt:out std_logic;
          out1:inout std_logic_vector(3 downto 0));
end geweidecord;
architecture one of geweidecord is
     signal a:std_logic_vector(9 downto 0);
     signal b:std_logic_vector(3 downto 0);
begin
     a<=key9 & key8 & key7 & key6 & key5 & key4 & key3 & key2 & key1 & key0; 
     process(a)
     begin
          case a is 
                  when "1111111111" =>b<="0000";
                  when "1111111110" =>b<="0001";
                  when "1111111101" =>b<="0010";
                  when "1111111011" =>b<="0011";
                  when "1111110111" =>b<="0100";
                  when "1111101111" =>b<="0101";
                  when "1111011111" =>b<="0110";
                  when "1110111111" =>b<="0111";
                  when "1101111111" =>b<="1000";
                  when "1011111111" =>b<="1001";
                  when "0111111111" =>b<="1010";
                  when others       =>b<="0000";
         end case;
     end process;
     out1<=b;
     bt<=b(3) or b(2) or b(1) or b(0);
end one;