LIBRARY IEEE;
USE ieee.std_logic_1164.all;

entity add is
	port
  	(
		x:in std_logic_vector(3 downto 0); --部分積1011
		s:in std_logic_vector(3 downto 0); --pA1011
		l:in std_logic; --單個乘數0
		m:in std_logic; --上個單個加法器的結果的進位0
		j:out std_logic;--本次單個加法器的結果的進位
		k:out std_logic; --整個結果的順序低位
		z:out std_logic_vector(3 downto 0) --單個加法器的結果
	);
end add;

architecture behave0 of add is
	signal n: std_logic;
	signal y:std_logic_vector(3 downto 0);
	begin
	process(x,s,l,m)
	begin
		y<=s;
		if(l='0') then
			y<="0000";
		end if;
		k<=x(0);
		n<='0';
		
		for i in 0 to 2 loop
			z(i)<=x(i+1) xor y(i) xor n;
			if(((x(i+1) and y(i)) or (x(i+1) and n) or (y(i) and n))='1') then
				n<='1';
			else n<='0';
			end if;
		end loop;
        	z(3)<=n xor m xor y(3);
        	if(((m and y(3)) or (m and n) or (y(3) and n))='1') then 
				j<='1';
		else j<='0';
		end if;
	end process;
end behave0;
					 	
LIBRARY IEEE;
USE ieee.std_logic_1164.all;

ENTITY plus IS
	port
	(
		pA	:in std_logic_vector(3 downto 0);
		pB	:in std_logic_vector(3 downto 0);
		result	:out std_logic_vector(7 downto 0)
	);
end plus;



ARCHITECTURE behave OF plus IS
	component add
		port
  		(
			x:in std_logic_vector(3 downto 0);
			s:in std_logic_vector(3 downto 0);
		    l:in std_logic;
			m:in std_logic;
			j:out std_logic;
			k:out std_logic;
			z:out std_logic_vector(3 downto 0)
		 );
	end component;
	signal v0,v1,v2,v3,v4:std_logic_vector(3 downto 0);
	signal d0,d1,d2,d3:std_logic;
begin
	d0<='0';
	v0<=pA when(pB(0)='1') else "0000";
	v4<=pA;
	uq1:add port map(v0,v4,pB(1),d0,d1,result(0),v1);
	uq2:add port map(v1,v4,pB(2),d1,d2,result(1),v2);
	uq3:add port map(v2,v4,pB(3),d2,d3,result(2),v3);
	result(3)<=v3(0);result(4)<=v3(1);result(5)<=v3(2);result(6)<=v3(3);result(7)<=d3;
end behave;