?? disasm_debug.v
字號:
`include "timescale.v"
module testbench();
reg rst;
reg clk;
reg [3:0] ins_len;
reg [31:0] opcode, opcode2;
reg [7:0] mem [0:16'h1FFF];
reg [7:0] ip_next;
always #20 clk = ~clk;
always @ (posedge clk) begin
ip_next = ip_next+ins_len;
opcode[7:0] <= mem[ip_next+3];
opcode[15:8] <= mem[ip_next+2];
opcode[23:16] <= mem[ip_next+1];
opcode[31:24] <= mem[ip_next];
opcode2[7:0] <= mem[ip_next+7];
opcode2[15:8] <= mem[ip_next+6];
opcode2[23:16] <= mem[ip_next+5];
opcode2[31:24] <= mem[ip_next+4];
// $display("opcode = %h",mem[ip_next]);
end
initial begin
$display("80386 start->");
$readmemh("prom.mem.v", mem, 0, 100);
ip_next[7:0] = 0;
ins_len = 0;
rst = 0;
clk = 0;
opcode[7:0] <= mem[ip_next+3];
opcode[15:8] <= mem[ip_next+2];
opcode[23:16] <= mem[ip_next+1];
opcode[31:24] <= mem[ip_next];
repeat(2) @(posedge clk);
rst = 1;
repeat(2) @(posedge clk);
repeat(1) @(negedge clk);
rst = 0;
repeat(180) @(posedge clk);
$display("done!");
$dumpvars;
$finish;
end
always @ (negedge clk) begin
casex (opcode)
32'b01100111????????????????????????: begin /* address size */
ins_len = 1;
end
32'b11110000????????????????????????: begin /* LOCK */
ins_len = 1;
end
32'b01100110????????????????????????: begin /* operand size */
ins_len = 1;
end
32'b00101110????????????????????????: begin /* CS segment override */
ins_len = 1;
end
32'b00111110????????????????????????: begin /* DS segment override */
ins_len = 1;
end
32'b00100110????????????????????????: begin /* ES segment override */
ins_len = 1;
end
32'b01100100????????????????????????: begin /* FS segment override */
ins_len = 1;
end
32'b01100101????????????????????????: begin /* GS segment override */
ins_len = 1;
end
32'b00110110????????????????????????: begin /* SS segment override */
ins_len = 1;
end
32'b00110111????????????????????????: begin /* AAA 1 */
ins_len = 1;
$display("AAA");
end
32'b1101010100001010????????????????: begin /* AAD 2 */
ins_len = 2;
$display("AAD");
end
32'b1101010000001010????????????????: begin /* AAM 2 */
ins_len = 2;
$display("AAM");
end
32'b00111111????????????????????????: begin /* AAS 1 */
ins_len = 1;
$display("AAS");
end
32'b0001000?11??????????????????????: begin /* ADC 2 reg1 to reg2 */
ins_len = 2;
$display("ADC r1,r2");
end
32'b0001001?11??????????????????????: begin /* ADC 2 reg2 to reg1 */
ins_len = 2;
$display("ADC r2,r1");
end
32'b0001001?????????????????????????: begin /* ADC 2 mem to reg */
ins_len = 2;
$display("ADC mem,r");
end
32'b0001000?????????????????????????: begin /* ADC 2 reg to mem */
ins_len = 2;
$display("ADC r,mem");
end
32'b100000??11010???????????????????: begin /* ADC 3 immediate to reg */
ins_len = 4;
$display("ADC #,r");
end
32'b0001010?????????????????????????: begin /* ADC 2 immediage to AL,AX or EAX */
ins_len = 3;
$display("ADC #,EAX");
end
32'b100000????010???????????????????: begin /* ADC 3 immediage to mem */
ins_len = 4;
$display("ADC #,mem");
end
32'b0000000?11??????????????????????: begin /* ADD 2 reg1 to reg2 */
ins_len = 2;
$display("ADD r1,r2");
end
32'b0000001?11??????????????????????: begin /* ADD 2 reg2 to reg1 */
ins_len = 2;
$display("ADD r2,r1");
end
32'b0000001?????????????????????????: begin /* ADD 2 mem to reg */
ins_len = 2;
$display("ADD mem,r");
end
32'b0000000?????????????????????????: begin /* ADD 2 reg to mem */
ins_len = 2;
$display("ADD r,mem");
end
32'b100000??11000???????????????????: begin /* ADD 3 immediate to reg */
ins_len = 4;
$display("ADD #,r");
end
32'b0000010?????????????????????????: begin /* ADD 2 imediate to AL,AX,or EAX */
ins_len = 3;
$display("ADD #,EAX");
end
32'b100000????000???????????????????: begin /* ADD 3 imediate to mem */
ins_len = 4;
$display("ADD #,mem");
end
32'b0010000?11??????????????????????: begin /* AND 2 reg1 to reg2 */
ins_len = 2;
$display("AND r1,r2");
end
32'b0010001?11??????????????????????: begin /* AND 2 reg2 to reg1 */
ins_len = 2;
$display("AND r2,r1");
end
32'b0010001?????????????????????????: begin /* AND 2 mem to reg */
ins_len = 2;
$display("AND mem,r");
end
32'b0010000?????????????????????????: begin /* AND 2 reg to mem */
ins_len = 2;
$display("AND r,mem");
end
32'b100000??11100???????????????????: begin /* AND 3 immediate to reg */
ins_len = 4;
$display("AND #,r");
end
32'b0010010?????????????????????????: begin /* AND 2 immediate to AL,AX,EAX */
ins_len = 3;
$display("AND #,EAX");
end
32'b100000????100???????????????????: begin /* AND 3 immediate to mem */
ins_len = 4;
$display("AND #,mem");
end
32'b0110001111??????????????????????: begin /* ARPL 2 from reg */
ins_len = 2;
$display("ARPL r");
end
32'b01100011????????????????????????: begin /* ARPL 2 from mem */
ins_len = 2;
$display("ARPL mem");
end
32'b01100010????????????????????????: begin /* BOUND 2 */
ins_len = 2;
$display("BOUND");
end
32'b000011111011110011??????????????: begin /* BSF 3 reg1,reg2 */
ins_len = 3;
$display("BSF r1,r2");
end
32'b0000111110111100????????????????: begin /* BSF 3 mem,reg */
ins_len = 3;
$display("BSF mem,r");
end
32'b000011111011110111??????????????: begin /* BSR 3 reg1,reg2 */
ins_len = 3;
$display("BSR r1,r2");
end
32'b0000111110111101????????????????: begin /* BSR 3 mem,reg */
ins_len = 3;
$display("BSR mem,r");
end
32'b0000111111001???????????????????: begin /* BSWAP 2 */
ins_len = 2;
$display("BSWAP");
end
32'b000011111011101011100???????????: begin /* BT 4 reg,immediate */
ins_len = 4;
$display("BT r,#");
end
32'b0000111110111010???100??????????: begin /* BT 4 mem,immediate */
ins_len = 4;
$display("BT mem,#");
end
32'b000011111010001111??????????????: begin /* BT 3 reg1,reg2 */
ins_len = 3;
$display("BT r1,r2");
end
32'b0000111110100011????????????????: begin /* BT 3 mem,reg */
ins_len = 3;
$display("BT mem,r");
end
32'b000011111011101011111???????????: begin /* BTC 4 reg,immediate */
ins_len = 4;
$display("BTC r,#");
end
32'b0000111110111010???111??????????: begin /* BTC 4 mem,immediate */
ins_len = 4;
$display("BTC mem,#");
end
32'b000011111011101111??????????????: begin /* BTC 3 reg1,reg2 */
ins_len = 3;
$display("BTC r1,r2");
end
32'b0000111110111011????????????????: begin /* BTC 3 mem,reg */
ins_len = 3;
$display("BTC mem,r");
end
32'b000011111011101011110???????????: begin /* BTR 4 reg,immediate */
ins_len = 4;
$display("BTR r,#");
end
32'b0000111110111010???110??????????: begin /* BTR 4 mem,immediate */
ins_len = 4;
$display("BTR mem,#");
end
32'b000011111011001111??????????????: begin /* BTR 3 reg1,reg2 */
ins_len = 3;
$display("BTR r1,r2");
end
32'b0000111110110011????????????????: begin /* BTR 3 mem,reg */
ins_len = 3;
$display("BTR mem,r");
end
32'b000011111011101011101???????????: begin /* BTS 4 reg,immediate */
ins_len = 4;
$display("BTS r,#");
end
32'b0000111110111010???101??????????: begin /* BTS 4 mem,immediate */
ins_len = 4;
$display("BTS mem,#");
end
32'b000011111010101111??????????????: begin /* BTS 3 reg1,reg2 */
ins_len = 3;
$display("BTS r1,r2");
end
32'b0000111110101011????????????????: begin /* BTS 3 mem,reg */
ins_len = 3;
$display("BTS mem,r");
end
32'b11101000????????????????????????: begin /* CALL 3 same segment direct */
ins_len = 3;
$display("CALL");
end
32'b1111111111010???????????????????: begin /* CALL 2 same segment reg indirect */
ins_len = 2;
$display("CALL");
end
32'b11111111???010??????????????????: begin /* CALL 2 same segment mem indirect */
ins_len = 2;
$display("CALL");
end
32'b10011010????????????????????????: begin /* CALL 2 other segment direct */
ins_len = 2;
$display("CALL");
end
32'b11111111???011??????????????????: begin /* CALL 2 other segment indirect */
ins_len = 2;
$display("CALL");
end
32'b10011000????????????????????????: begin /* CBW 1 */
ins_len = 1;
$display("CBW");
end
32'b10011001????????????????????????: begin /* CDQ 1 */
ins_len = 1;
$display("CDQ");
end
32'b11111000????????????????????????: begin /* CLC 1 */
ins_len = 1;
$display("CLC");
end
32'b11111100????????????????????????: begin /* CLD 1 */
ins_len = 1;
$display("CLD");
end
32'b11111010????????????????????????: begin /* CLI 1 */
ins_len = 1;
$display("CLI");
end
32'b0000111100000110????????????????: begin /* CLTS 2 */
ins_len = 2;
$display("CLTS");
end
32'b11110101????????????????????????: begin /* CMC 1 */
ins_len = 1;
$display("CMC");
end
32'b0011100?11??????????????????????: begin /* CMP 2 reg1 reg2 */
ins_len = 2;
$display("CMP r1,r2");
end
32'b0011101?11??????????????????????: begin /* CMP 2 reg2 reg1 */
ins_len = 2;
$display("CMP r2,r1");
end
32'b0011100?????????????????????????: begin /* CMP 2 mem reg */
ins_len = 2;
$display("CMP mem,r");
end
32'b0011101?????????????????????????: begin /* CMP 2 reg mem */
ins_len = 2;
$display("CMP r,mem");
end
32'b100000??11111???????????????????: begin /* CMP 3 immediate reg */
ins_len = 3;
$display("CMP #,r");
end
32'b0011110?????????????????????????: begin /* CMP 2 immediate with AL,AX or EAX */
ins_len = 2;
$display("CMP #,EAX");
end
32'b100000?????111??????????????????: begin /* CMP 3 immedaite with mem */
ins_len = 3;
$display("CMP #,mem");
end
32'b1010011?????????????????????????: begin /* CMPS 1 */
ins_len = 1;
$display("CMPS");
end
32'b000011111011000?11??????????????: begin /* CMPXCHG 3 reg1,reg2 */
ins_len = 3;
$display("CMPXCHG r1,r2");
end
32'b000011111011000?????????????????: begin /* CMPXCHG 3 mem,reg */
ins_len = 3;
$display("CMPXCHG mem,r");
end
32'b0000111110100010????????????????: begin /* CPUID 2 */
ins_len = 2;
$display("CPUID");
end
32'b10011001????????????????????????: begin /* CWD 1 */
ins_len = 1;
$display("CWD");
end
32'b10011000????????????????????????: begin /* CWDE 1 */
ins_len = 1;
$display("CWDE");
end
32'b00100111????????????????????????: begin /* DAA 1 */
ins_len = 1;
$display("DAA");
end
32'b00101111????????????????????????: begin /* DAS 1 */
ins_len = 1;
$display("DAS");
end
32'b1111111?11001???????????????????: begin /* DEC 2 reg */
ins_len = 2;
$display("DEC r");
end
32'b01001???????????????????????????: begin /* DEC 1 reg(altmeate encoding) */
ins_len = 1;
$display("DEC r");
end
32'b1111111????001??????????????????: begin /* DEC 2 */
ins_len = 2;
$display("DEC");
end
32'b1111011?11110???????????????????: begin /* DIV 2 AL,AX,EAX by reg */
ins_len = 2;
$display("DIV EAX,r");
end
32'b1111011????110??????????????????: begin /* DIV 2 AL,AX,EAX by mem */
ins_len = 2;
$display("DIV EAX,mem");
end
32'b11001000????????????????????????: begin /* ENTER 4 */
ins_len = 4;
$display("ENTER");
end
32'b11110100????????????????????????: begin /* HLT 1 */
ins_len = 1;
$display("HLT");
end
32'b1111011?11111???????????????????: begin /* IDIV 2 AL,AX,EAX by reg */
ins_len = 2;
$display("IDIV EAX,r");
end
32'b1111011????111??????????????????: begin /* IDIV 2 AL,AX,EAX by mem */
ins_len = 2;
$display("IDIV EAX,mem");
end
32'b1111011?11101???????????????????: begin /* IMUL 2 AL,AX,EAX with reg */
ins_len = 2;
$display("IMUL EAX,r");
end
32'b1111011????101??????????????????: begin /* IMUL 2 AL,AX,EAX with mem */
ins_len = 2;
$display("IMUL EAX,mem");
end
32'b0000111110101111????????????????: begin /* IMUL 3 reg1 with reg2 */
ins_len = 3;
$display("IMUL r1,r2");
end
32'b0000111110101111????????????????: begin /* IMUL 3 reg with mem */
ins_len = 3;
$display("IMUL r,mem");
end
32'b011010?111??????????????????????: begin /* IMUL 3 reg1 with immediate to reg2 */
ins_len = 3;
$display("IMUL r1,#,r2");
end
32'b011010?1????????????????????????: begin /* IMUL 3 mem with immediate to reg */
ins_len = 3;
$display("IMUL mem,#,r");
end
32'b1110010?????????????????????????: begin /* IN 2 fixed port */
ins_len = 2;
$display("IN");
end
32'b1110110?????????????????????????: begin /* IN 2 varable port */
ins_len = 2;
$display("IN");
end
32'b1111111?11000???????????????????: begin /* INC 2 reg */
ins_len = 2;
$display("INC r");
end
32'b01000???????????????????????????: begin /* INC 1 reg(alternate encoding) */
ins_len = 1;
$display("INC r");
end
32'b1111111????000??????????????????: begin /* INC 2 mem */
ins_len = 2;
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