// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"


module testbench();

// Inputs
    reg rst;
    reg clk;
    reg debug;
    reg [63:0] dbg_code;
    reg [63:0] dbg_code1;


// Outputs
    wire [15:0] ip;
    wire [15:0] ip_next;
    wire [15:0] sp;
    wire [15:0] bp;
    wire [15:0] si;
    wire [15:0] di;
    wire [15:0] cs;
    wire [15:0] ds;
    wire [15:0] ss;
    wire [15:0] es;
    wire [15:0] ax;
    wire [15:0] bx;
    wire [15:0] cx;
    wire [15:0] dx;
    wire [15:0] flags;
    wire [19:0] a;
    wire [31:0] aluresult;
    
    wire [`a86_icode_width-1:0] icode;

    wire stalled;	

// Bidirs

wire iobus_we;
wire iobus_ce;

wire iobus_clk;
wire iobus_rst;
reg iobus_busy2core;

wire [`a86_io_awidth-1:0] iobus_addr;
wire [1:0] iobus_be;
wire [`a86_io_dwidth-1:0] iobus_data_out;
reg [`a86_io_dwidth*`a86_io_num_devices-1:0] iobus_data_in;

reg [`a86_io_num_devices-1:0] iobus_busy;

wire [15:0] core_data_out;


// Instantiate the UUT
    a86_verilog_top uut (
    .rst(rst), 
    .clk(clk), 
    .debug(debug), 
    .dbg_code(dbg_code), 
    .ip(ip), 
    .ip_next(ip_next), 
    .stalled(stalled),
    .sp(sp), 
    .bp(bp), 
    .si(si), 
    .di(di), 
    .cs(cs), 
    .ds(ds), 
    .ss(ss), 
    .es(es), 
    .ax(ax), 
    .bx(bx), 
    .cx(cx), 
    .dx(dx), 
    .flags(flags), 
    .a(a),
    .aluresult(aluresult),
    .icode(icode),

    .iobus_clk( iobus_clk ), 
    .iobus_rst( iobus_rst ), 
    .iobus_we( iobus_we ), 
    .iobus_ce( iobus_ce ), 
    .iobus_addr( iobus_addr), 
    .iobus_be( iobus_be ), 
    .iobus_data_out( iobus_data_out ), 
    .iobus_data_in( iobus_data_in ), 
    .iobus_busy( iobus_busy )
        );

reg [7:0] mem [0:16'h1FFF]; 

always #20 clk = ~clk;



// imitate ROM Cache fetches!


always @ (posedge clk) begin
   dbg_code[7:0] <= `a86_d_romfetch mem[ip_next];
   dbg_code[15:8] <= `a86_d_romfetch mem[ip_next+1];
   dbg_code[23:16] <= `a86_d_romfetch mem[ip_next+2];
   dbg_code[31:24] <= `a86_d_romfetch mem[ip_next+3];
   dbg_code[47:32] <= `a86_d_romfetch mem[ip_next+4];
end
/*
always @ (ip_next) begin
   dbg_code1[7:0] = `a86_d_romfetch mem[ip_next];
   dbg_code1[15:8] = `a86_d_romfetch mem[ip_next+1];
   dbg_code1[23:16] = `a86_d_romfetch mem[ip_next+2];
   dbg_code1[31:24] = `a86_d_romfetch mem[ip_next+3];
   dbg_code1[47:32] = `a86_d_romfetch mem[ip_next+4];
end
*/

always @ (posedge clk) begin
  #8
  
`include "a86_disasm.inc"

   $display("ALU %h, stalled? %b", aluresult,stalled);

   $display("AX BX CX DX %h %h %h %h %b", ax, bx, cx, dx, flags);
   $display("SP BP SI DI EA %h %h %h %h %h", sp, bp, si, di, a);
   $display("CS DS ES SS %h %h %h %h", cs, ds, es, ss);

end


always @ (posedge clk) begin
  #4;

 if (icode[`a86_icode_inout]) begin
   if (icode[`a86_icode_in]) begin
    $display("*** IO RD [%h] %h", iobus_addr, iobus_data_in[15:0]);
   end 

   if (icode[`a86_icode_out]) begin
    $display("*** IO WR [%h] %h", iobus_addr, iobus_data_out);
   end 
 end


end



integer i; 

initial begin
   $display("a86->");
   $readmemh("prom.mem.v", mem, 0, 100); 

   // all devices are ready ?
   iobus_busy = 3'b000;

   rst = 0;
   clk = 0;
   iobus_data_in[47:0] = 48'h0000_0000_1255;

   dbg_code[7:0] = mem[0];
   dbg_code[15:8] = mem[1];
   dbg_code[23:16] = mem[2];
   dbg_code[31:24] = mem[3];
   dbg_code[47:32] = mem[4];

   debug = 1; // debug mode !!

//   $monitor("%t %h %h %h %h %h %b",$time,rst, clk,ip, ip_next, dbg_code[31:0], mem[ip_next]);    

   repeat(2)	@(posedge clk); 
   rst = 1;
   repeat(2)	@(posedge clk);
   repeat(1)	@(negedge clk);
   rst = 0;
   repeat(180)	@(posedge clk);

/*
  for (i=0; i<20; i=i+1) begin
    repeat(1)	@(posedge clk);
    #1;
  end
*/
  $display("done!");



  $dumpvars; 


  $finish;

end




endmodule