library train;
use train.cntpkg.all;


library ieee;
use ieee.std_logic_1164.all;
  

entity cnt is
  port
     (nreset,load,ci,clk:in std_logic;
      d      :in   std_logic_vector(7 downto 0);
      co     :out  std_logic;
       q1    :out  std_logic_vector(6 downto 0);
       q2    :out  std_logic_vector(6 downto 0));
end cnt;
 
architecture arch of cnt is
signal qa,qb  :  std_logic_vector(3 downto 0);
begin 
  u1:cont60 port map(ci,nreset,load,d,clk,co,qa,qb);
  u2:decode47 port map(qa,q1);
  u3:decode47 port map(qb,q2);

end arch;