?? vga.fit.rpt
字號:
Fitter report for vga
Tue May 06 15:24:30 2008
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
; Fitter Status ; Successful - Tue May 06 15:24:30 2008 ;
; Quartus II Version ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name ; vga ;
; Top-level Entity Name ; vga ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 80 / 240 ( 33 % ) ;
; Total pins ; 19 / 80 ( 24 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Use smart compilation ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/芯片學習/FPGA學習/液晶資料/080505_vga/vga.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/芯片學習/FPGA學習/液晶資料/080505_vga/vga.pin.
+------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total logic elements ; 80 / 240 ( 33 % ) ;
; -- Combinational with no register ; 42 ;
; -- Register only ; 3 ;
; -- Combinational with a register ; 35 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 31 ;
; -- 3 input functions ; 5 ;
; -- 2 input functions ; 36 ;
; -- 1 input functions ; 7 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 54 ;
; -- arithmetic mode ; 26 ;
; -- qfbk mode ; 5 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 6 ;
; -- asynchronous clear/load mode ; 13 ;
; ; ;
; Total LABs ; 11 / 24 ( 46 % ) ;
; Logic elements in carry chains ; 30 ;
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