-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY vga IS 
	port
	(
		CLK :  IN  STD_LOGIC;
		vSync :  OUT  STD_LOGIC;
		CKV :  OUT  STD_LOGIC;
		OEV :  OUT  STD_LOGIC;
		VCOM :  OUT  STD_LOGIC;
		DMOD :  OUT  STD_LOGIC;
		OEH :  OUT  STD_LOGIC;
		hSync :  OUT  STD_LOGIC;
		B_OUT :  OUT  STD_LOGIC_VECTOR(1 downto 0);
		CPH :  OUT  STD_LOGIC_VECTOR(2 downto 0);
		G_OUT :  OUT  STD_LOGIC_VECTOR(2 downto 0);
		R_OUT :  OUT  STD_LOGIC_VECTOR(2 downto 0)
	);
END vga;

ARCHITECTURE bdf_type OF vga IS 

component lcd_drv
	PORT(N_RST : IN STD_LOGIC;
		 CLK24M : IN STD_LOGIC;
		 DISEN : IN STD_LOGIC;
		 DISMOD : IN STD_LOGIC;
		 R : IN STD_LOGIC;
		 G : IN STD_LOGIC;
		 B : IN STD_LOGIC;
		 FIFO_EMPTY : IN STD_LOGIC;
		 vSync : IN STD_LOGIC;
		 hSync : IN STD_LOGIC;
		 CKV : OUT STD_LOGIC;
		 OEV : OUT STD_LOGIC;
		 VCOM : OUT STD_LOGIC;
		 DMOD : OUT STD_LOGIC;
		 OEH : OUT STD_LOGIC;
		 SAM_CLK : OUT STD_LOGIC;
		 B_OUT : OUT STD_LOGIC_VECTOR(1 downto 0);
		 CPH : OUT STD_LOGIC_VECTOR(2 downto 0);
		 G_OUT : OUT STD_LOGIC_VECTOR(2 downto 0);
		 R_OUT : OUT STD_LOGIC_VECTOR(2 downto 0)
	);
end component;

component vgasingl
	PORT(CLK : IN STD_LOGIC;
		 MD : IN STD_LOGIC;
		 HS : OUT STD_LOGIC;
		 VS : OUT STD_LOGIC;
		 R : OUT STD_LOGIC;
		 G : OUT STD_LOGIC;
		 B : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;


BEGIN 
vSync <= SYNTHESIZED_WIRE_4;
VCOM <= SYNTHESIZED_WIRE_6;
hSync <= SYNTHESIZED_WIRE_5;
SYNTHESIZED_WIRE_3 <= '0';



b2v_inst : lcd_drv
PORT MAP(CLK24M => CLK,
		 R => SYNTHESIZED_WIRE_0,
		 G => SYNTHESIZED_WIRE_1,
		 B => SYNTHESIZED_WIRE_2,
		 FIFO_EMPTY => SYNTHESIZED_WIRE_3,
		 vSync => SYNTHESIZED_WIRE_4,
		 hSync => SYNTHESIZED_WIRE_5,
		 CKV => CKV,
		 OEV => OEV,
		 VCOM => SYNTHESIZED_WIRE_6,
		 DMOD => DMOD,
		 OEH => OEH,
		 B_OUT => B_OUT,
		 CPH => CPH,
		 G_OUT => G_OUT,
		 R_OUT => R_OUT);

b2v_inst1 : vgasingl
PORT MAP(CLK => CLK,
		 MD => SYNTHESIZED_WIRE_6,
		 HS => SYNTHESIZED_WIRE_5,
		 VS => SYNTHESIZED_WIRE_4,
		 R => SYNTHESIZED_WIRE_0,
		 G => SYNTHESIZED_WIRE_1,
		 B => SYNTHESIZED_WIRE_2);

END;