?? cntr_f0g.tdf
字號:
--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="MAX II" lpm_port_updown="PORT_USED" lpm_width=16 clock q updown CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.1 cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_counter 2007:03:22:23:17:10:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION maxii_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin0_used, cin1_used, cin_used, lut_mask, operation_mode, output_mode, power_up, register_cascade_mode, sum_lutc_input, synch_mode, x_on_violation)
RETURNS ( combout, cout, regout);
--synthesis_resources = lut 16
SUBDESIGN cntr_f0g
(
clock : input;
q[15..0] : output;
updown : input;
)
VARIABLE
counter_cella0 : maxii_lcell
WITH (
cin_used = "false",
lut_mask = "5599",
operation_mode = "arithmetic",
synch_mode = "on"
);
counter_cella1 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella2 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella3 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella4 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella5 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella6 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella7 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella8 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella9 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella10 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella11 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella12 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella13 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella14 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella15 : maxii_lcell
WITH (
cin_used = "true",
lut_mask = "5A90",
operation_mode = "normal",
sum_lutc_input = "cin",
synch_mode = "on"
);
aclr : NODE;
aclr_actual : WIRE;
clk_en : NODE;
cnt_en : NODE;
data[15..0] : NODE;
s_val[15..0] : WIRE;
safe_q[15..0] : WIRE;
sclr : NODE;
sload : NODE;
sset : NODE;
updownDir : WIRE;
BEGIN
counter_cella[15..0].aclr = aclr_actual;
counter_cella[15..0].aload = B"0000000000000000";
counter_cella[1].cin = counter_cella[0].cout;
counter_cella[2].cin = counter_cella[1].cout;
counter_cella[3].cin = counter_cella[2].cout;
counter_cella[4].cin = counter_cella[3].cout;
counter_cella[5].cin = counter_cella[4].cout;
counter_cella[6].cin = counter_cella[5].cout;
counter_cella[7].cin = counter_cella[6].cout;
counter_cella[8].cin = counter_cella[7].cout;
counter_cella[9].cin = counter_cella[8].cout;
counter_cella[10].cin = counter_cella[9].cout;
counter_cella[11].cin = counter_cella[10].cout;
counter_cella[12].cin = counter_cella[11].cout;
counter_cella[13].cin = counter_cella[12].cout;
counter_cella[14].cin = counter_cella[13].cout;
counter_cella[15].cin = counter_cella[14].cout;
counter_cella[15..0].clk = clock;
counter_cella[15..0].dataa = safe_q[];
counter_cella[15..0].datab = updownDir;
counter_cella[15..0].datac = ((sset & s_val[]) # ((! sset) & data[]));
counter_cella[15].datad = B"1";
counter_cella[15..0].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
counter_cella[15..0].sclr = sclr;
counter_cella[15..0].sload = (sset # sload);
aclr = GND;
aclr_actual = aclr;
clk_en = VCC;
cnt_en = VCC;
data[] = GND;
q[] = safe_q[];
s_val[] = B"1111111111111111";
safe_q[] = counter_cella[15..0].regout;
sclr = GND;
sload = GND;
sset = GND;
updownDir = updown;
END;
--VALID FILE
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