{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLKIN " "Info: Assuming node \"CLKIN\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 264 560 728 280 "CLKIN" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLKIN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 248 -144 24 264 "WR" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A15 " "Info: Assuming node \"A15\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 24 -168 0 40 "A15" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A15" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A1 " "Info: Assuming node \"A1\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -200 -232 -64 -184 "A1" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A3 " "Info: Assuming node \"A3\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -136 -232 -64 -120 "A3" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A14 " "Info: Assuming node \"A14\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 8 -168 0 24 "A14" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A14" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A0 " "Info: Assuming node \"A0\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -232 -232 -64 -216 "A0" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A2 " "Info: Assuming node \"A2\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -168 -232 -64 -152 "A2" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "A2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ADC_CLK " "Info: Assuming node \"ADC_CLK\" is an undefined clock" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -168 2048 2216 -152 "ADC_CLK" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADC_CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}