# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		M2_0610_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY ZHUHAI
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:47:27  DECEMBER 12, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VHDL -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name DEVICE_MIGRATION_LIST EPM240T100C5
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_73 -to A0
set_location_assignment PIN_74 -to A1
set_location_assignment PIN_75 -to A2
set_location_assignment PIN_61 -to A14
set_location_assignment PIN_72 -to WR
set_location_assignment PIN_71 -to RD
set_location_assignment PIN_14 -to CO1
set_location_assignment PIN_18 -to CO5
set_location_assignment PIN_19 -to CO6
set_location_assignment PIN_52 -to F2
set_location_assignment PIN_35 -to AL_CL2
set_location_assignment PIN_42 -to HM1
set_location_assignment PIN_48 -to SERDY1
set_location_assignment PIN_15 -to D[7]
set_location_assignment PIN_16 -to D[6]
set_location_assignment PIN_17 -to D[5]
set_location_assignment PIN_26 -to D[4]
set_location_assignment PIN_27 -to D[3]
set_location_assignment PIN_28 -to D[2]
set_location_assignment PIN_29 -to D[1]
set_location_assignment PIN_34 -to D[0]
set_location_assignment PIN_12 -to CLKIN
set_location_assignment PIN_53 -to QF1
set_location_assignment PIN_77 -to A3
set_location_assignment PIN_47 -to LMT_A
set_location_assignment PIN_43 -to LMT_B
set_location_assignment PIN_51 -to PUL
set_location_assignment PIN_55 -to Test1
set_location_assignment PIN_54 -to QZ1
set_location_assignment PIN_56 -to XINT2
set_location_assignment PIN_49 -to QF2
set_location_assignment PIN_7 -to TDRIB
set_location_assignment PIN_6 -to CIN1
set_location_assignment PIN_5 -to CIN2
set_location_assignment PIN_4 -to CIN3
set_location_assignment PIN_3 -to CIN4
set_location_assignment PIN_2 -to CIN5
set_location_assignment PIN_1 -to CIN6
set_location_assignment PIN_33 -to KIN
set_location_assignment PIN_30 -to ADC_DATA
set_location_assignment PIN_36 -to SIN
set_location_assignment PIN_41 -to XIN
set_global_assignment -name BDF_FILE ZHUHAI.bdf
set_global_assignment -name BDF_FILE PULSE_GEN.bdf
set_global_assignment -name BDF_FILE WATCH_DOG.bdf
set_global_assignment -name BDF_FILE Filter.bdf
set_global_assignment -name BDF_FILE QEP_CNT.bdf
set_global_assignment -name BDF_FILE ../../../Xiaoxin2/output.bdf