?? jia.vhd
字號:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY jia IS
PORT (op1, op2 : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0);)
END jia;
ARCHITECTURE mm OF jia IS
BEGIN
result <= op1 + op2;
END mm;
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