LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY jia IS
	PORT (op1, op2		: in std_logic_vector(7 downto 0);
		   
           result       : out std_logic_vector(7 downto 0);)
END jia;

ARCHITECTURE mm OF jia IS
BEGIN
	result <= op1 + op2;
    END mm;