library IEEE;
            use IEEE.std_logic_1164.all;
            use ieee.std_logic_unsigned.all;

            entity jian is
            port (
            A: in STD_LOGIC_vector(7 downto 0);
            aout: out STD_LOGIC_vector(7 downto 0)
            );
            end jian;

            architecture mmm of jian is
            begin

            aout<="01111111"-A;
            end mmm;