Timing Analyzer report for uart
Mon Jan 07 10:42:32 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'sel[2]'
  7. Clock Setup: 'sel[0]'
  8. Clock Setup: 'sel[1]'
  9. Clock Hold: 'clk'
 10. tsu
 11. tco
 12. th
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                    ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+--------------------------------+-----------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                           ; To                                      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+--------------------------------+-----------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 10.612 ns                                      ; sel[1]                         ; uart:inst|uart_receiver:inst|RDR[2]     ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 25.988 ns                                      ; uart:inst|br_gen:inst2|ctr3[2] ; txd_doneH                               ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 5.082 ns                                       ; rst_n                          ; scan:inst6|bin[3]                       ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 45.09 MHz ( period = 22.177 ns )               ; uart:inst|br_gen:inst2|ctr3[2] ; uart:inst|uart_transmitter:inst1|bct[1] ; clk        ; clk      ; 0            ;
; Clock Setup: 'sel[1]'        ; N/A                                      ; None          ; 236.13 MHz ( period = 4.235 ns )               ; uart:inst|br_gen:inst2|ctr3[2] ; uart:inst|br_gen:inst2|ctr3[2]          ; sel[1]     ; sel[1]   ; 0            ;
; Clock Setup: 'sel[0]'        ; N/A                                      ; None          ; 286.70 MHz ( period = 3.488 ns )               ; uart:inst|br_gen:inst2|ctr3[2] ; uart:inst|br_gen:inst2|ctr3[2]          ; sel[0]     ; sel[0]   ; 0            ;
; Clock Setup: 'sel[2]'        ; N/A                                      ; None          ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; uart:inst|br_gen:inst2|ctr3[2] ; uart:inst|br_gen:inst2|ctr3[2]          ; sel[2]     ; sel[2]   ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; scan:inst6|min_one[1]          ; scan:inst6|bin[1]                       ; clk        ; clk      ; 19           ;
; Total number of failed paths ;                                          ;               ;                                                ;                                ;                                         ;            ;          ; 19           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+--------------------------------+-----------------------------------------+------------+----------+--------------+