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?? uart.fit.eqn

?? quatus II 環(huán)境下vhdl實現(xiàn)RS232功能
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--G1_bct[1] is uart:inst|uart_transmitter:u3|bct[1] at LC_X1_Y10_N4
--operation mode is normal

G1_bct[1]_lut_out = GND;
G1_bct[1] = DFFEAS(G1_bct[1]_lut_out, GLOBAL(clk), rst_n, , , G1L4, , , VCC);


--G1_bct[3] is uart:inst|uart_transmitter:u3|bct[3] at LC_X2_Y10_N9
--operation mode is normal

G1_bct[3]_lut_out = G1L01 & G1L02 # !G1L91 # !G1_state.tdata;
G1_bct[3] = DFFEAS(G1_bct[3]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--G1_bct[0] is uart:inst|uart_transmitter:u3|bct[0] at LC_X2_Y10_N2
--operation mode is normal

G1_bct[0]_lut_out = G1L1 & G1L02 # !G1_state.tdata # !G1L91;
G1_bct[0] = DFFEAS(G1_bct[0]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--G1L02 is uart:inst|uart_transmitter:u3|reduce_or~34 at LC_X2_Y10_N4
--operation mode is normal

G1_bct[2]_qfbk = G1_bct[2];
G1L02 = G1_bct[1] # G1_bct[2]_qfbk # !G1_bct[3] # !G1_bct[0];

--G1_bct[2] is uart:inst|uart_transmitter:u3|bct[2] at LC_X2_Y10_N4
--operation mode is normal

G1_bct[2] = DFFEAS(G1L02, GLOBAL(clk), rst_n, , , G1L7, , , VCC);


--G1_state.tdata is uart:inst|uart_transmitter:u3|state.tdata at LC_X2_Y10_N7
--operation mode is normal

G1_state.tdata_lut_out = G1L91 & G1_state.synch # G1L02 & G1_state.tdata # !G1L91 & G1_state.tdata;
G1_state.tdata = DFFEAS(G1_state.tdata_lut_out, GLOBAL(clk), rst_n, , , , , , );


--E1_ctr3[2] is uart:inst|br_gen:u1|ctr3[2] at LC_X1_Y10_N3
--operation mode is normal

E1_ctr3[2]_lut_out = !E1_ctr3[2];
E1_ctr3[2] = DFFEAS(E1_ctr3[2]_lut_out, GLOBAL(E1L91), VCC, , E1L1, , , , );


--G1L91 is uart:inst|uart_transmitter:u3|nextstate.tdata~91 at LC_X1_Y10_N0
--operation mode is normal

G1L91 = !G1_bclk_dlayed & E1_ctr3[2];


--G1_tsr[0] is uart:inst|uart_transmitter:u3|tsr[0] at LC_X2_Y10_N6
--operation mode is normal

G1_tsr[0]_lut_out = !G1L81 & G1L91 & G1_state.synch # !G1L53;
G1_tsr[0] = DFFEAS(G1_tsr[0]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--D1_com_mten is scan:inst6|com_mten at LC_X1_Y5_N3
--operation mode is normal

D1_com_mten_lut_out = D1_sel[0] & D1_sel[1];
D1_com_mten = DFFEAS(D1_com_mten_lut_out, GLOBAL(K1_safe_q[13]), rst_n, , , , , , );


--D1_com_mone is scan:inst6|com_mone at LC_X1_Y5_N2
--operation mode is normal

D1_com_mone_lut_out = !D1_sel[0] & D1_sel[1];
D1_com_mone = DFFEAS(D1_com_mone_lut_out, GLOBAL(K1_safe_q[13]), rst_n, , , , , , );


--D1_com_sten is scan:inst6|com_sten at LC_X1_Y5_N6
--operation mode is normal

D1_com_sten_lut_out = D1_sel[0] & !D1_sel[1];
D1_com_sten = DFFEAS(D1_com_sten_lut_out, GLOBAL(K1_safe_q[13]), rst_n, , , , , , );


--D1_com_sone is scan:inst6|com_sone at LC_X1_Y5_N4
--operation mode is normal

D1_com_sone_lut_out = !D1_sel[0] & !D1_sel[1];
D1_com_sone = DFFEAS(D1_com_sone_lut_out, GLOBAL(K1_safe_q[13]), rst_n, , , , , , );


--D1_bin[0] is scan:inst6|bin[0] at LC_X3_Y5_N8
--operation mode is normal

D1_bin[0]_lut_out = D1L32 & D1_min_ten[0] # !D1_sel[0] # !D1L32 & D1_sel[0] & D1_sec_ten[0];
D1_bin[0] = DFFEAS(D1_bin[0]_lut_out, GLOBAL(K1_safe_q[13]), VCC, , rst_n, , , , );


--D1_bin[1] is scan:inst6|bin[1] at LC_X3_Y4_N4
--operation mode is normal

D1_bin[1]_lut_out = D1_sel[1] & D1L22 & D1_min_ten[1] # !D1L22 & D1_min_one[1] # !D1_sel[1] & D1L22;
D1_bin[1] = DFFEAS(D1_bin[1]_lut_out, GLOBAL(K1_safe_q[13]), VCC, , rst_n, , , , );


--D1_bin[2] is scan:inst6|bin[2] at LC_X3_Y5_N5
--operation mode is normal

D1_bin[2]_lut_out = D1L12 & D1_min_ten[2] # !D1_sel[0] # !D1L12 & D1_sec_ten[2] & D1_sel[0];
D1_bin[2] = DFFEAS(D1_bin[2]_lut_out, GLOBAL(K1_safe_q[13]), VCC, , rst_n, , , , );


--D1_bin[3] is scan:inst6|bin[3] at LC_X3_Y4_N3
--operation mode is normal

D1_bin[3]_lut_out = D1_sel[1] & D1L02 & D1_min_ten[3] # !D1L02 & D1_min_one[3] # !D1_sel[1] & D1L02;
D1_bin[3] = DFFEAS(D1_bin[3]_lut_out, GLOBAL(K1_safe_q[13]), VCC, , rst_n, , , , );


--D1L34 is scan:inst6|seven_seg[6]~82 at LC_X3_Y4_N7
--operation mode is normal

D1L34 = D1_bin[0] & D1_bin[3] # D1_bin[1] $ D1_bin[2] # !D1_bin[0] & D1_bin[1] # D1_bin[2] $ D1_bin[3];


--D1L24 is scan:inst6|seven_seg[5]~84 at LC_X3_Y4_N0
--operation mode is normal

D1L24 = D1_bin[1] & !D1_bin[3] & D1_bin[0] # !D1_bin[2] # !D1_bin[1] & D1_bin[0] & D1_bin[2] $ !D1_bin[3];


--D1L14 is scan:inst6|seven_seg[4]~86 at LC_X3_Y4_N5
--operation mode is normal

D1L14 = D1_bin[1] & D1_bin[0] & !D1_bin[3] # !D1_bin[1] & D1_bin[2] & !D1_bin[3] # !D1_bin[2] & D1_bin[0];


--D1L04 is scan:inst6|seven_seg[3]~88 at LC_X3_Y4_N6
--operation mode is normal

D1L04 = D1_bin[1] & D1_bin[0] & D1_bin[2] # !D1_bin[0] & !D1_bin[2] & D1_bin[3] # !D1_bin[1] & !D1_bin[3] & D1_bin[0] $ D1_bin[2];


--D1L93 is scan:inst6|seven_seg[2]~90 at LC_X3_Y4_N8
--operation mode is normal

D1L93 = D1_bin[2] & D1_bin[3] & D1_bin[1] # !D1_bin[0] # !D1_bin[2] & D1_bin[1] & !D1_bin[0] & !D1_bin[3];


--D1L83 is scan:inst6|seven_seg[1]~92 at LC_X3_Y4_N9
--operation mode is normal

D1L83 = D1_bin[1] & D1_bin[0] & D1_bin[3] # !D1_bin[0] & D1_bin[2] # !D1_bin[1] & D1_bin[2] & D1_bin[0] $ D1_bin[3];


--D1L73 is scan:inst6|seven_seg[0]~94 at LC_X3_Y4_N2
--operation mode is normal

D1L73 = D1_bin[2] & !D1_bin[1] & D1_bin[0] $ !D1_bin[3] # !D1_bin[2] & D1_bin[0] & D1_bin[1] $ !D1_bin[3];


--J1_safe_q[5] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[5] at LC_X3_Y7_N5
--operation mode is arithmetic

J1_safe_q[5]_carry_eqn = (!J1L41 & GND) # (J1L41 & VCC);
J1_safe_q[5]_lut_out = J1_safe_q[5] $ (J1_safe_q[5]_carry_eqn);
J1_safe_q[5] = DFFEAS(J1_safe_q[5]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L81 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella5~COUT at LC_X3_Y7_N5
--operation mode is arithmetic

J1L81_cout_0 = !J1L41 # !J1_safe_q[5];
J1L81 = CARRY(J1L81_cout_0);

--J1L91 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella5~COUTCOUT1_3 at LC_X3_Y7_N5
--operation mode is arithmetic

J1L91_cout_1 = !J1L41 # !J1_safe_q[5];
J1L91 = CARRY(J1L91_cout_1);


--J1_safe_q[6] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[6] at LC_X3_Y7_N6
--operation mode is arithmetic

J1_safe_q[6]_carry_eqn = (!J1L41 & J1L81) # (J1L41 & J1L91);
J1_safe_q[6]_lut_out = J1_safe_q[6] $ (!J1_safe_q[6]_carry_eqn);
J1_safe_q[6] = DFFEAS(J1_safe_q[6]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L12 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella6~COUT at LC_X3_Y7_N6
--operation mode is arithmetic

J1L12_cout_0 = J1_safe_q[6] & !J1L81;
J1L12 = CARRY(J1L12_cout_0);

--J1L22 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella6~COUTCOUT1_3 at LC_X3_Y7_N6
--operation mode is arithmetic

J1L22_cout_1 = J1_safe_q[6] & !J1L91;
J1L22 = CARRY(J1L22_cout_1);


--J1_safe_q[4] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[4] at LC_X3_Y7_N4
--operation mode is arithmetic

J1_safe_q[4]_lut_out = J1_safe_q[4] $ (!J1L11);
J1_safe_q[4] = DFFEAS(J1_safe_q[4]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L41 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella4~COUT at LC_X3_Y7_N4
--operation mode is arithmetic

J1L41 = J1L51;


--E1L71 is uart:inst|br_gen:u1|bclkx8~23 at LC_X1_Y7_N1
--operation mode is normal

E1L71 = sel[0] & sel[1] # !sel[0] & sel[1] & J1_safe_q[6] # !sel[1] & J1_safe_q[4];


--J1_safe_q[7] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[7] at LC_X3_Y7_N7
--operation mode is normal

J1_safe_q[7]_carry_eqn = (!J1L41 & J1L12) # (J1L41 & J1L22);
J1_safe_q[7]_lut_out = J1_safe_q[7] $ J1_safe_q[7]_carry_eqn;
J1_safe_q[7] = DFFEAS(J1_safe_q[7]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );


--E1L81 is uart:inst|br_gen:u1|bclkx8~24 at LC_X1_Y7_N2
--operation mode is normal

E1L81 = sel[0] & E1L71 & J1_safe_q[7] # !E1L71 & J1_safe_q[5] # !sel[0] & E1L71;


--J1_safe_q[2] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[2] at LC_X3_Y7_N2
--operation mode is arithmetic

J1_safe_q[2]_lut_out = J1_safe_q[2] $ !J1L5;
J1_safe_q[2] = DFFEAS(J1_safe_q[2]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L8 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella2~COUT at LC_X3_Y7_N2
--operation mode is arithmetic

J1L8_cout_0 = J1_safe_q[2] & !J1L5;
J1L8 = CARRY(J1L8_cout_0);

--J1L9 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella2~COUTCOUT1_3 at LC_X3_Y7_N2
--operation mode is arithmetic

J1L9_cout_1 = J1_safe_q[2] & !J1L6;
J1L9 = CARRY(J1L9_cout_1);


--J1_safe_q[1] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[1] at LC_X3_Y7_N1
--operation mode is arithmetic

J1_safe_q[1]_lut_out = J1_safe_q[1] $ J1L2;
J1_safe_q[1] = DFFEAS(J1_safe_q[1]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L5 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella1~COUT at LC_X3_Y7_N1
--operation mode is arithmetic

J1L5_cout_0 = !J1L2 # !J1_safe_q[1];
J1L5 = CARRY(J1L5_cout_0);

--J1L6 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella1~COUTCOUT1_3 at LC_X3_Y7_N1
--operation mode is arithmetic

J1L6_cout_1 = !J1L3 # !J1_safe_q[1];
J1L6 = CARRY(J1L6_cout_1);


--J1_safe_q[0] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[0] at LC_X3_Y7_N0
--operation mode is arithmetic

J1_safe_q[0]_lut_out = !J1_safe_q[0];
J1_safe_q[0] = DFFEAS(J1_safe_q[0]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L2 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella0~COUT at LC_X3_Y7_N0
--operation mode is arithmetic

J1L2_cout_0 = J1_safe_q[0];
J1L2 = CARRY(J1L2_cout_0);

--J1L3 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella0~COUTCOUT1_3 at LC_X3_Y7_N0
--operation mode is arithmetic

J1L3_cout_1 = J1_safe_q[0];
J1L3 = CARRY(J1L3_cout_1);


--E1L51 is uart:inst|br_gen:u1|bclkx8~21 at LC_X1_Y7_N6
--operation mode is normal

E1L51 = sel[0] & sel[1] # J1_safe_q[1] # !sel[0] & !sel[1] & J1_safe_q[0];


--J1_safe_q[3] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[3] at LC_X3_Y7_N3
--operation mode is arithmetic

J1_safe_q[3]_lut_out = J1_safe_q[3] $ (J1L8);
J1_safe_q[3] = DFFEAS(J1_safe_q[3]_lut_out, GLOBAL(E1_cnt2), VCC, , , , , , );

--J1L11 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella3~COUT at LC_X3_Y7_N3
--operation mode is arithmetic

J1L11_cout_0 = !J1L8 # !J1_safe_q[3];
J1L11 = CARRY(J1L11_cout_0);

--J1L21 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella3~COUTCOUT1_1 at LC_X3_Y7_N3
--operation mode is arithmetic

J1L21_cout_1 = !J1L9 # !J1_safe_q[3];
J1L21 = CARRY(J1L21_cout_1);


--E1L61 is uart:inst|br_gen:u1|bclkx8~22 at LC_X1_Y7_N7
--operation mode is normal

E1L61 = sel[1] & E1L51 & J1_safe_q[3] # !E1L51 & J1_safe_q[2] # !sel[1] & E1L51;


--F1_bclkx8_rising is uart:inst|uart_receiver:u2|bclkx8_rising at LC_X1_Y7_N3
--operation mode is normal

F1_bclkx8_dlayed_qfbk = F1_bclkx8_dlayed;
F1_bclkx8_rising = !F1_bclkx8_dlayed_qfbk & sel[2] & E1L81 # !sel[2] & E1L61;

--F1_bclkx8_dlayed is uart:inst|uart_receiver:u2|bclkx8_dlayed at LC_X1_Y7_N3
--operation mode is normal

F1_bclkx8_dlayed = DFFEAS(F1_bclkx8_rising, GLOBAL(clk), rst_n, , , E1L91, , , VCC);


--F1_ct1[2] is uart:inst|uart_receiver:u2|ct1[2] at LC_X1_Y6_N6
--operation mode is normal

F1_ct1[2]_lut_out = !F1L51 & F1_ct1[2] $ (F1_ct1[1] & F1L1);
F1_ct1[2] = DFFEAS(F1_ct1[2]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1_ct1[1] is uart:inst|uart_receiver:u2|ct1[1] at LC_X1_Y6_N1
--operation mode is normal

F1_ct1[1]_lut_out = !F1L51 & F1_ct1[1] $ (F1_ct1[0] & F1L52);
F1_ct1[1] = DFFEAS(F1_ct1[1]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1_ct1[0] is uart:inst|uart_receiver:u2|ct1[0] at LC_X1_Y6_N8
--operation mode is normal

F1_ct1[0]_lut_out = !F1L51 & F1_ct1[0] $ F1L52;
F1_ct1[0] = DFFEAS(F1_ct1[0]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1L23 is uart:inst|uart_receiver:u2|ok_en~52 at LC_X1_Y7_N4
--operation mode is normal

F1L23 = F1_ct1[1] & F1_ct1[0] & F1_ct1[2] & F1_bclkx8_rising;


--F1_state.recv_data is uart:inst|uart_receiver:u2|state.recv_data at LC_X2_Y6_N2
--operation mode is normal

F1_state.recv_data_lut_out = F1L92 # F1_state.recv_data & F1L84 # !F1L23;
F1_state.recv_data = DFFEAS(F1_state.recv_data_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1_ct2[1] is uart:inst|uart_receiver:u2|ct2[1] at LC_X2_Y7_N2
--operation mode is normal

F1_ct2[1]_lut_out = GND;
F1_ct2[1] = DFFEAS(F1_ct2[1]_lut_out, GLOBAL(clk), rst_n, , , F1L5, , , VCC);


--F1_ct2[0] is uart:inst|uart_receiver:u2|ct2[0] at LC_X2_Y7_N1
--operation mode is normal

F1_ct2[0]_lut_out = GND;
F1_ct2[0] = DFFEAS(F1_ct2[0]_lut_out, GLOBAL(clk), rst_n, , , F1L2, , , VCC);


--F1_ct2[3] is uart:inst|uart_receiver:u2|ct2[3] at LC_X2_Y7_N4
--operation mode is normal

F1_ct2[3]_lut_out = F1L11 & F1L84 # !F1L23 # !F1_state.recv_data;
F1_ct2[3] = DFFEAS(F1_ct2[3]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1L84 is uart:inst|uart_receiver:u2|reduce_or~36 at LC_X2_Y7_N5
--operation mode is normal

F1_ct2[2]_qfbk = F1_ct2[2];
F1L84 = F1_ct2[1] # F1_ct2[2]_qfbk # F1_ct2[0] # !F1_ct2[3];

--F1_ct2[2] is uart:inst|uart_receiver:u2|ct2[2] at LC_X2_Y7_N5
--operation mode is normal

F1_ct2[2] = DFFEAS(F1L84, GLOBAL(clk), rst_n, , , F1L8, , , VCC);


--F1L33 is uart:inst|uart_receiver:u2|ok_en~53 at LC_X1_Y7_N0
--operation mode is normal

F1L33 = rxd & F1_state.recv_data & F1L23 & !F1L84;

--F1_rxd_readyH is uart:inst|uart_receiver:u2|rxd_readyH at LC_X1_Y7_N0
--operation mode is normal

F1_rxd_readyH = DFFEAS(F1L33, GLOBAL(clk), VCC, , rst_n, , , , );


--G1L7 is uart:inst|uart_transmitter:u3|add~43 at LC_X1_Y10_N7
--operation mode is arithmetic

G1L7 = G1_bct[2] $ (!G1L5);

--G1L8 is uart:inst|uart_transmitter:u3|add~43COUT at LC_X1_Y10_N7
--operation mode is arithmetic

G1L8_cout_0 = G1_bct[2] & !G1L5;
G1L8 = CARRY(G1L8_cout_0);

--G1L9 is uart:inst|uart_transmitter:u3|add~43COUTCOUT1_52 at LC_X1_Y10_N7
--operation mode is arithmetic

G1L9_cout_1 = G1_bct[2] & !G1L6;
G1L9 = CARRY(G1L9_cout_1);


--G1L4 is uart:inst|uart_transmitter:u3|add~42 at LC_X1_Y10_N6
--operation mode is arithmetic

G1L4 = G1_bct[1] $ (G1L2);

--G1L5 is uart:inst|uart_transmitter:u3|add~42COUT at LC_X1_Y10_N6
--operation mode is arithmetic

G1L5_cout_0 = !G1L2 # !G1_bct[1];
G1L5 = CARRY(G1L5_cout_0);

--G1L6 is uart:inst|uart_transmitter:u3|add~42COUTCOUT1_50 at LC_X1_Y10_N6
--operation mode is arithmetic

G1L6_cout_1 = !G1L3 # !G1_bct[1];
G1L6 = CARRY(G1L6_cout_1);


--G1L01 is uart:inst|uart_transmitter:u3|add~44 at LC_X1_Y10_N8
--operation mode is normal

G1L01 = G1_bct[3] $ G1L8;

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