--F1_RDR[3] is uart:inst|uart_receiver:u2|RDR[3] at LC_X2_Y8_N5
--operation mode is normal

F1_RDR[3]_lut_out = !F1_RSR[3];
F1_RDR[3] = DFFEAS(F1_RDR[3]_lut_out, GLOBAL(clk), rst_n, , F1L33, , , , );


--E1_cnt1[3] is uart:inst|br_gen:u1|cnt1[3] at LC_X5_Y7_N3
--operation mode is normal

E1_cnt1[3]_lut_out = E1L11 & E1L33 # !E1_cnt1[4];
E1_cnt1[3] = DFFEAS(E1_cnt1[3]_lut_out, GLOBAL(clk), VCC, , , , , , );


--E1_cnt1[1] is uart:inst|br_gen:u1|cnt1[1] at LC_X5_Y7_N4
--operation mode is normal

E1_cnt1[1]_lut_out = E1L5 & E1L33 # !E1_cnt1[4];
E1_cnt1[1] = DFFEAS(E1_cnt1[1]_lut_out, GLOBAL(clk), VCC, , , , , , );


--E1L62 is uart:inst|br_gen:u1|cnt1[4]~185 at LC_X5_Y7_N1
--operation mode is normal

E1_cnt1[2]_qfbk = E1_cnt1[2];
E1L62 = E1_cnt1[0] & !E1_cnt1[1] & E1_cnt1[2]_qfbk & E1_cnt1[3];

--E1_cnt1[2] is uart:inst|br_gen:u1|cnt1[2] at LC_X5_Y7_N1
--operation mode is normal

E1_cnt1[2] = DFFEAS(E1L62, GLOBAL(clk), VCC, , , E1L8, , , VCC);


--E1_cnt1[4] is uart:inst|br_gen:u1|cnt1[4] at LC_X5_Y7_N0
--operation mode is normal

E1_cnt1[4]_lut_out = E1L41 & E1L33 # !E1_cnt1[4];
E1_cnt1[4] = DFFEAS(E1_cnt1[4]_lut_out, GLOBAL(clk), VCC, , , , , , );


--E1L33 is uart:inst|br_gen:u1|reduce_nor~36 at LC_X5_Y7_N2
--operation mode is normal

E1_cnt1[0]_qfbk = E1_cnt1[0];
E1L33 = E1_cnt1[0]_qfbk # E1_cnt1[2] # !E1_cnt1[1] # !E1_cnt1[3];

--E1_cnt1[0] is uart:inst|br_gen:u1|cnt1[0] at LC_X5_Y7_N2
--operation mode is normal

E1_cnt1[0] = DFFEAS(E1L33, GLOBAL(clk), VCC, , , E1L2, , , VCC);


--E1L23 is uart:inst|br_gen:u1|process0~0 at LC_X6_Y7_N2
--operation mode is normal

E1L23 = E1_cnt1[4] & !E1L33 # !E1_cnt1[4] & E1L62;


--F1L03 is uart:inst|uart_receiver:u2|nextstate.start_detected~165 at LC_X1_Y5_N7
--operation mode is normal

F1L03 = F1_state.start_detected & !F1_bclkx8_rising;


--F1L13 is uart:inst|uart_receiver:u2|nextstate.start_detected~166 at LC_X1_Y6_N7
--operation mode is normal

F1L13 = F1_state.start_detected & F1_ct1[2] # !F1_ct1[1] # !F1_ct1[0];


--F1_state.idle is uart:inst|uart_receiver:u2|state.idle at LC_X1_Y5_N8
--operation mode is normal

F1_state.idle_lut_out = !F1L72 & F1_state.recv_data # F1L03 # !rxd;
F1_state.idle = DFFEAS(F1_state.idle_lut_out, GLOBAL(clk), rst_n, , , , , , );


--F1L62 is uart:inst|uart_receiver:u2|inc2~4 at LC_X2_Y7_N0
--operation mode is normal

F1L62 = F1L84 & F1_state.recv_data & F1L23;


--G1_tsr[3] is uart:inst|uart_transmitter:u3|tsr[3] at LC_X2_Y9_N9
--operation mode is normal

G1_tsr[3]_lut_out = G1L81 & !F1_RDR[2] # !G1L81 & G1_tsr[4];
G1_tsr[3] = DFFEAS(G1_tsr[3]_lut_out, GLOBAL(clk), rst_n, , G1L82, , , , );


--F1_RSR[0] is uart:inst|uart_receiver:u2|RSR[0] at LC_X2_Y8_N3
--operation mode is normal

F1_RSR[0]_lut_out = F1_RSR[1];
F1_RSR[0] = DFFEAS(F1_RSR[0]_lut_out, GLOBAL(clk), VCC, , F1L15, , , , );


--F1_RSR[4] is uart:inst|uart_receiver:u2|RSR[4] at LC_X2_Y7_N3
--operation mode is normal

F1_RSR[4]_lut_out = F1_RSR[5];
F1_RSR[4] = DFFEAS(F1_RSR[4]_lut_out, GLOBAL(clk), VCC, , F1L15, , , , );


--F1_RSR[5] is uart:inst|uart_receiver:u2|RSR[5] at LC_X2_Y4_N5
--operation mode is normal

F1_RSR[5]_lut_out = GND;
F1_RSR[5] = DFFEAS(F1_RSR[5]_lut_out, GLOBAL(clk), VCC, , F1L15, F1_RSR[6], , , VCC);


--F1_RSR[1] is uart:inst|uart_receiver:u2|RSR[1] at LC_X2_Y8_N1
--operation mode is normal

F1_RSR[1]_lut_out = GND;
F1_RSR[1] = DFFEAS(F1_RSR[1]_lut_out, GLOBAL(clk), VCC, , F1L15, F1_RSR[2], , , VCC);


--F1_RSR[6] is uart:inst|uart_receiver:u2|RSR[6] at LC_X2_Y4_N0
--operation mode is normal

F1_RSR[6]_lut_out = F1_RSR[7];
F1_RSR[6] = DFFEAS(F1_RSR[6]_lut_out, GLOBAL(clk), VCC, , F1L15, , , , );


--F1_RSR[2] is uart:inst|uart_receiver:u2|RSR[2] at LC_X2_Y8_N4
--operation mode is normal

F1_RSR[2]_lut_out = F1_RSR[3];
F1_RSR[2] = DFFEAS(F1_RSR[2]_lut_out, GLOBAL(clk), VCC, , F1L15, , , , );


--F1_RSR[7] is uart:inst|uart_receiver:u2|RSR[7] at LC_X2_Y4_N2
--operation mode is normal

F1_RSR[7]_lut_out = rxd;
F1_RSR[7] = DFFEAS(F1_RSR[7]_lut_out, GLOBAL(clk), VCC, , F1L15, , , , );


--F1_RSR[3] is uart:inst|uart_receiver:u2|RSR[3] at LC_X2_Y8_N9
--operation mode is normal

F1_RSR[3]_lut_out = GND;
F1_RSR[3] = DFFEAS(F1_RSR[3]_lut_out, GLOBAL(clk), VCC, , F1L15, F1_RSR[4], , , VCC);


--E1L11 is uart:inst|br_gen:u1|add~126 at LC_X5_Y7_N8
--operation mode is arithmetic

E1L11 = E1_cnt1[3] $ (E1L9);

--E1L21 is uart:inst|br_gen:u1|add~126COUT at LC_X5_Y7_N8
--operation mode is arithmetic

E1L21_cout_0 = !E1L9 # !E1_cnt1[3];
E1L21 = CARRY(E1L21_cout_0);

--E1L31 is uart:inst|br_gen:u1|add~126COUTCOUT1_145 at LC_X5_Y7_N8
--operation mode is arithmetic

E1L31_cout_1 = !E1L01 # !E1_cnt1[3];
E1L31 = CARRY(E1L31_cout_1);


--E1L8 is uart:inst|br_gen:u1|add~125 at LC_X5_Y7_N7
--operation mode is arithmetic

E1L8 = E1_cnt1[2] $ !E1L6;

--E1L9 is uart:inst|br_gen:u1|add~125COUT at LC_X5_Y7_N7
--operation mode is arithmetic

E1L9_cout_0 = E1_cnt1[2] & !E1L6;
E1L9 = CARRY(E1L9_cout_0);

--E1L01 is uart:inst|br_gen:u1|add~125COUTCOUT1_143 at LC_X5_Y7_N7
--operation mode is arithmetic

E1L01_cout_1 = E1_cnt1[2] & !E1L7;
E1L01 = CARRY(E1L01_cout_1);


--E1L2 is uart:inst|br_gen:u1|add~123 at LC_X5_Y7_N5
--operation mode is arithmetic

E1L2 = !E1_cnt1[0];

--E1L3 is uart:inst|br_gen:u1|add~123COUT at LC_X5_Y7_N5
--operation mode is arithmetic

E1L3_cout_0 = E1_cnt1[0];
E1L3 = CARRY(E1L3_cout_0);

--E1L4 is uart:inst|br_gen:u1|add~123COUTCOUT1_140 at LC_X5_Y7_N5
--operation mode is arithmetic

E1L4_cout_1 = E1_cnt1[0];
E1L4 = CARRY(E1L4_cout_1);


--E1L5 is uart:inst|br_gen:u1|add~124 at LC_X5_Y7_N6
--operation mode is arithmetic

E1L5 = E1_cnt1[1] $ E1L3;

--E1L6 is uart:inst|br_gen:u1|add~124COUT at LC_X5_Y7_N6
--operation mode is arithmetic

E1L6_cout_0 = !E1L3 # !E1_cnt1[1];
E1L6 = CARRY(E1L6_cout_0);

--E1L7 is uart:inst|br_gen:u1|add~124COUTCOUT1_141 at LC_X5_Y7_N6
--operation mode is arithmetic

E1L7_cout_1 = !E1L4 # !E1_cnt1[1];
E1L7 = CARRY(E1L7_cout_1);


--E1L41 is uart:inst|br_gen:u1|add~127 at LC_X5_Y7_N9
--operation mode is normal

E1L41 = E1_cnt1[4] $ !E1L21;


--F1L72 is uart:inst|uart_receiver:u2|nextstate.idle~226 at LC_X1_Y7_N8
--operation mode is normal

F1L72 = F1_state.recv_data & F1L23 & !F1L84;


--G1_tsr[4] is uart:inst|uart_transmitter:u3|tsr[4] at LC_X2_Y9_N2
--operation mode is normal

G1_tsr[4]_lut_out = G1L81 & F1_RDR[3] # !G1L81 & G1_tsr[5];
G1_tsr[4] = DFFEAS(G1_tsr[4]_lut_out, GLOBAL(clk), rst_n, , G1L82, , , , );


--F1L15 is uart:inst|uart_receiver:u2|RSR[0]~7 at LC_X1_Y7_N5
--operation mode is normal

F1L15 = rst_n & F1_state.recv_data & F1L84 & F1L23;


--G1_tsr[5] is uart:inst|uart_transmitter:u3|tsr[5] at LC_X2_Y9_N8
--operation mode is normal

G1_tsr[5]_lut_out = G1L81 & !F1_RDR[4] # !G1L81 & G1_tsr[6];
G1_tsr[5] = DFFEAS(G1_tsr[5]_lut_out, GLOBAL(clk), rst_n, , G1L82, , , , );


--G1_tsr[6] is uart:inst|uart_transmitter:u3|tsr[6] at LC_X2_Y9_N4
--operation mode is normal

G1_tsr[6]_lut_out = G1L81 & F1_RDR[5] # !G1L81 & G1_tsr[7];
G1_tsr[6] = DFFEAS(G1_tsr[6]_lut_out, GLOBAL(clk), rst_n, , G1L82, , , , );


--G1_tsr[7] is uart:inst|uart_transmitter:u3|tsr[7] at LC_X2_Y10_N3
--operation mode is normal

G1_tsr[7]_lut_out = G1L81 & !F1_RDR[6] # !G1L81 & G1_tsr[8];
G1_tsr[7] = DFFEAS(G1_tsr[7]_lut_out, GLOBAL(clk), rst_n, , G1L82, , , , );


--G1_tsr[8] is uart:inst|uart_transmitter:u3|tsr[8] at LC_X2_Y10_N0
--operation mode is normal

G1_tsr[8]_lut_out = G1L81 & !F1_RDR[7] # !G1L81 & G1_tsr[8] & !G1L63;
G1_tsr[8] = DFFEAS(G1_tsr[8]_lut_out, GLOBAL(clk), rst_n, , , , , , );


--G1L63 is uart:inst|uart_transmitter:u3|tsr~838 at LC_X2_Y10_N8
--operation mode is normal

G1L63 = G1L02 & !G1_state.synch & G1_state.tdata & G1L91;


--G1L73 is uart:inst|uart_transmitter:u3|txd_doneH~1 at LC_X1_Y10_N9
--operation mode is normal

G1L73 = G1L02 # G1_bclk_dlayed # !E1_ctr3[2] # !G1_state.tdata;


--F1L92 is uart:inst|uart_receiver:u2|nextstate.recv_data~189 at LC_X2_Y6_N1
--operation mode is normal

F1L92 = !rxd & F1L74 & F1_bclkx8_rising & F1_state.start_detected;


--sel[0] is sel[0] at PIN_16
--operation mode is input

sel[0] = INPUT();


--sel[1] is sel[1] at PIN_21
--operation mode is input

sel[1] = INPUT();


--sel[2] is sel[2] at PIN_22
--operation mode is input

sel[2] = INPUT();


--rxd is rxd at PIN_49
--operation mode is input

rxd = INPUT();


--clk is clk at PIN_18
--operation mode is input

clk = INPUT();


--rst_n is rst_n at PIN_23
--operation mode is input

rst_n = INPUT();


--txd_startH is txd_startH at PIN_24
--operation mode is input

txd_startH = INPUT();


--rxd_readyH is rxd_readyH at PIN_1
--operation mode is output

rxd_readyH = OUTPUT(F1_rxd_readyH);


--txd_doneH is txd_doneH at PIN_2
--operation mode is output

txd_doneH = OUTPUT(!G1L73);


--txd is txd at PIN_45
--operation mode is output

txd = OUTPUT(!G1_tsr[0]);


--dig4 is dig4 at PIN_32
--operation mode is output

dig4 = OUTPUT(D1_com_mten);


--dig3 is dig3 at PIN_31
--operation mode is output

dig3 = OUTPUT(D1_com_mone);


--dig2 is dig2 at PIN_30
--operation mode is output

dig2 = OUTPUT(D1_com_sten);


--dig1 is dig1 at PIN_29
--operation mode is output

dig1 = OUTPUT(D1_com_sone);


--seven_seg[7] is seven_seg[7] at PIN_44
--operation mode is output

seven_seg[7] = OUTPUT(GND);


--seven_seg[6] is seven_seg[6] at PIN_43
--operation mode is output

seven_seg[6] = OUTPUT(!D1L34);


--seven_seg[5] is seven_seg[5] at PIN_42
--operation mode is output

seven_seg[5] = OUTPUT(D1L24);


--seven_seg[4] is seven_seg[4] at PIN_41
--operation mode is output

seven_seg[4] = OUTPUT(D1L14);


--seven_seg[3] is seven_seg[3] at PIN_40
--operation mode is output

seven_seg[3] = OUTPUT(D1L04);


--seven_seg[2] is seven_seg[2] at PIN_39
--operation mode is output

seven_seg[2] = OUTPUT(D1L93);


--seven_seg[1] is seven_seg[1] at PIN_38
--operation mode is output

seven_seg[1] = OUTPUT(D1L83);


--seven_seg[0] is seven_seg[0] at PIN_37
--operation mode is output

seven_seg[0] = OUTPUT(D1L73);


--F1L63 is uart:inst|uart_receiver:u2|RDR[0]~32 at LC_X2_Y5_N5
--operation mode is normal

F1L63 = !F1_RDR[0];


--F1L83 is uart:inst|uart_receiver:u2|RDR[1]~33 at LC_X3_Y6_N0
--operation mode is normal

F1L83 = !F1_RDR[1];


--F1L14 is uart:inst|uart_receiver:u2|RDR[3]~34 at LC_X3_Y6_N6
--operation mode is normal

F1L14 = !F1_RDR[3];


--F1L44 is uart:inst|uart_receiver:u2|RDR[5]~35 at LC_X2_Y5_N0
--operation mode is normal

F1L44 = !F1_RDR[5];