--F1_rxd_readyH is uart:inst|uart_receiver:u2|rxd_readyH
--operation mode is normal

F1_rxd_readyH_lut_out = F1L03;
F1_rxd_readyH = DFFEAS(F1_rxd_readyH_lut_out, clk, VCC, , rst_n, , , , );


--G1_bct[2] is uart:inst|uart_transmitter:u3|bct[2]
--operation mode is normal

G1_bct[2]_lut_out = G1L5;
G1_bct[2] = DFFEAS(G1_bct[2]_lut_out, clk, rst_n, , , , , , );


--G1_bct[1] is uart:inst|uart_transmitter:u3|bct[1]
--operation mode is normal

G1_bct[1]_lut_out = G1L3;
G1_bct[1] = DFFEAS(G1_bct[1]_lut_out, clk, rst_n, , , , , , );


--G1_bct[3] is uart:inst|uart_transmitter:u3|bct[3]
--operation mode is normal

G1_bct[3]_lut_out = G1L7 & G1L71 # !G1L61 # !G1_state.tdata;
G1_bct[3] = DFFEAS(G1_bct[3]_lut_out, clk, rst_n, , , , , , );


--G1_bct[0] is uart:inst|uart_transmitter:u3|bct[0]
--operation mode is normal

G1_bct[0]_lut_out = G1L1 & G1L71 # !G1L61 # !G1_state.tdata;
G1_bct[0] = DFFEAS(G1_bct[0]_lut_out, clk, rst_n, , , , , , );


--G1L71 is uart:inst|uart_transmitter:u3|reduce_or~34
--operation mode is normal

G1L71 = G1_bct[2] # G1_bct[1] # !G1_bct[0] # !G1_bct[3];


--G1_state.tdata is uart:inst|uart_transmitter:u3|state.tdata
--operation mode is normal

G1_state.tdata_lut_out = G1L61 & G1_state.synch # G1_state.tdata & G1L71 # !G1L61 & G1_state.tdata;
G1_state.tdata = DFFEAS(G1_state.tdata_lut_out, clk, rst_n, , , , , , );


--E1_ctr3[2] is uart:inst|br_gen:u1|ctr3[2]
--operation mode is normal

E1_ctr3[2]_lut_out = !E1_ctr3[2];
E1_ctr3[2] = DFFEAS(E1_ctr3[2]_lut_out, E1L51, VCC, , E1L1, , , , );


--G1_bclk_dlayed is uart:inst|uart_transmitter:u3|bclk_dlayed
--operation mode is normal

G1_bclk_dlayed_lut_out = E1_ctr3[2];
G1_bclk_dlayed = DFFEAS(G1_bclk_dlayed_lut_out, clk, rst_n, , , , , , );


--G1L61 is uart:inst|uart_transmitter:u3|nextstate.tdata~91
--operation mode is normal

G1L61 = E1_ctr3[2] & !G1_bclk_dlayed;


--G1_tsr[0] is uart:inst|uart_transmitter:u3|tsr[0]
--operation mode is normal

G1_tsr[0]_lut_out = !G1L51 & G1L61 & G1_state.synch # !G1L23;
G1_tsr[0] = DFFEAS(G1_tsr[0]_lut_out, clk, rst_n, , , , , , );


--D1_com_mten is scan:inst6|com_mten
--operation mode is normal

D1_com_mten_lut_out = D1_sel[1] & D1_sel[0];
D1_com_mten = DFFEAS(D1_com_mten_lut_out, K1_safe_q[13], rst_n, , , , , , );


--D1_com_mone is scan:inst6|com_mone
--operation mode is normal

D1_com_mone_lut_out = D1_sel[1] & !D1_sel[0];
D1_com_mone = DFFEAS(D1_com_mone_lut_out, K1_safe_q[13], rst_n, , , , , , );


--D1_com_sten is scan:inst6|com_sten
--operation mode is normal

D1_com_sten_lut_out = D1_sel[0] & !D1_sel[1];
D1_com_sten = DFFEAS(D1_com_sten_lut_out, K1_safe_q[13], rst_n, , , , , , );


--D1_com_sone is scan:inst6|com_sone
--operation mode is normal

D1_com_sone_lut_out = !D1_sel[1] & !D1_sel[0];
D1_com_sone = DFFEAS(D1_com_sone_lut_out, K1_safe_q[13], rst_n, , , , , , );


--D1_bin[0] is scan:inst6|bin[0]
--operation mode is normal

D1_bin[0]_lut_out = D1_sel[0] & D1L32 & D1_min_ten[0] # !D1L32 & D1_sec_ten[0] # !D1_sel[0] & D1L32;
D1_bin[0] = DFFEAS(D1_bin[0]_lut_out, K1_safe_q[13], VCC, , rst_n, , , , );


--D1_bin[1] is scan:inst6|bin[1]
--operation mode is normal

D1_bin[1]_lut_out = D1_sel[1] & D1L22 & D1_min_ten[1] # !D1L22 & D1_min_one[1] # !D1_sel[1] & D1L22;
D1_bin[1] = DFFEAS(D1_bin[1]_lut_out, K1_safe_q[13], VCC, , rst_n, , , , );


--D1_bin[2] is scan:inst6|bin[2]
--operation mode is normal

D1_bin[2]_lut_out = D1_sel[0] & D1L12 & D1_min_ten[2] # !D1L12 & D1_sec_ten[2] # !D1_sel[0] & D1L12;
D1_bin[2] = DFFEAS(D1_bin[2]_lut_out, K1_safe_q[13], VCC, , rst_n, , , , );


--D1_bin[3] is scan:inst6|bin[3]
--operation mode is normal

D1_bin[3]_lut_out = D1_sel[1] & D1L02 & D1_min_ten[3] # !D1L02 & D1_min_one[3] # !D1_sel[1] & D1L02;
D1_bin[3] = DFFEAS(D1_bin[3]_lut_out, K1_safe_q[13], VCC, , rst_n, , , , );


--D1L34 is scan:inst6|seven_seg[6]~82
--operation mode is normal

D1L34 = D1_bin[0] & D1_bin[3] # D1_bin[1] $ D1_bin[2] # !D1_bin[0] & D1_bin[1] # D1_bin[2] $ D1_bin[3];


--D1L24 is scan:inst6|seven_seg[5]~84
--operation mode is normal

D1L24 = D1_bin[0] & D1_bin[3] $ (D1_bin[1] # !D1_bin[2]) # !D1_bin[0] & D1_bin[1] & !D1_bin[2] & !D1_bin[3];


--D1L14 is scan:inst6|seven_seg[4]~86
--operation mode is normal

D1L14 = D1_bin[1] & D1_bin[0] & !D1_bin[3] # !D1_bin[1] & D1_bin[2] & !D1_bin[3] # !D1_bin[2] & D1_bin[0];


--D1L04 is scan:inst6|seven_seg[3]~88
--operation mode is normal

D1L04 = D1_bin[1] & D1_bin[0] & D1_bin[2] # !D1_bin[0] & !D1_bin[2] & D1_bin[3] # !D1_bin[1] & !D1_bin[3] & D1_bin[0] $ D1_bin[2];


--D1L93 is scan:inst6|seven_seg[2]~90
--operation mode is normal

D1L93 = D1_bin[2] & D1_bin[3] & D1_bin[1] # !D1_bin[0] # !D1_bin[2] & !D1_bin[0] & D1_bin[1] & !D1_bin[3];


--D1L83 is scan:inst6|seven_seg[1]~92
--operation mode is normal

D1L83 = D1_bin[1] & D1_bin[0] & D1_bin[3] # !D1_bin[0] & D1_bin[2] # !D1_bin[1] & D1_bin[2] & D1_bin[0] $ D1_bin[3];


--D1L73 is scan:inst6|seven_seg[0]~94
--operation mode is normal

D1L73 = D1_bin[2] & !D1_bin[1] & D1_bin[0] $ !D1_bin[3] # !D1_bin[2] & D1_bin[0] & D1_bin[1] $ !D1_bin[3];


--J1_safe_q[5] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[5]
--operation mode is arithmetic

J1_safe_q[5]_carry_eqn = J1L01;
J1_safe_q[5]_lut_out = J1_safe_q[5] $ (J1_safe_q[5]_carry_eqn);
J1_safe_q[5] = DFFEAS(J1_safe_q[5]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L21 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

J1L21 = CARRY(!J1L01 # !J1_safe_q[5]);


--J1_safe_q[6] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[6]
--operation mode is arithmetic

J1_safe_q[6]_carry_eqn = J1L21;
J1_safe_q[6]_lut_out = J1_safe_q[6] $ (!J1_safe_q[6]_carry_eqn);
J1_safe_q[6] = DFFEAS(J1_safe_q[6]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L41 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

J1L41 = CARRY(J1_safe_q[6] & !J1L21);


--J1_safe_q[4] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[4]
--operation mode is arithmetic

J1_safe_q[4]_carry_eqn = J1L8;
J1_safe_q[4]_lut_out = J1_safe_q[4] $ (!J1_safe_q[4]_carry_eqn);
J1_safe_q[4] = DFFEAS(J1_safe_q[4]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L01 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

J1L01 = CARRY(J1_safe_q[4] & !J1L8);


--E1L31 is uart:inst|br_gen:u1|bclkx8~23
--operation mode is normal

E1L31 = sel[0] & sel[1] # !sel[0] & sel[1] & J1_safe_q[6] # !sel[1] & J1_safe_q[4];


--J1_safe_q[7] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[7]
--operation mode is normal

J1_safe_q[7]_carry_eqn = J1L41;
J1_safe_q[7]_lut_out = J1_safe_q[7] $ (J1_safe_q[7]_carry_eqn);
J1_safe_q[7] = DFFEAS(J1_safe_q[7]_lut_out, E1_cnt2, VCC, , , , , , );


--E1L41 is uart:inst|br_gen:u1|bclkx8~24
--operation mode is normal

E1L41 = sel[0] & E1L31 & J1_safe_q[7] # !E1L31 & J1_safe_q[5] # !sel[0] & E1L31;


--J1_safe_q[2] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[2]
--operation mode is arithmetic

J1_safe_q[2]_carry_eqn = J1L4;
J1_safe_q[2]_lut_out = J1_safe_q[2] $ (!J1_safe_q[2]_carry_eqn);
J1_safe_q[2] = DFFEAS(J1_safe_q[2]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L6 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

J1L6 = CARRY(J1_safe_q[2] & !J1L4);


--J1_safe_q[1] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[1]
--operation mode is arithmetic

J1_safe_q[1]_carry_eqn = J1L2;
J1_safe_q[1]_lut_out = J1_safe_q[1] $ (J1_safe_q[1]_carry_eqn);
J1_safe_q[1] = DFFEAS(J1_safe_q[1]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L4 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

J1L4 = CARRY(!J1L2 # !J1_safe_q[1]);


--J1_safe_q[0] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[0]
--operation mode is arithmetic

J1_safe_q[0]_lut_out = !J1_safe_q[0];
J1_safe_q[0] = DFFEAS(J1_safe_q[0]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L2 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

J1L2 = CARRY(J1_safe_q[0]);


--E1L11 is uart:inst|br_gen:u1|bclkx8~21
--operation mode is normal

E1L11 = sel[1] & sel[0] # !sel[1] & sel[0] & J1_safe_q[1] # !sel[0] & J1_safe_q[0];


--J1_safe_q[3] is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|safe_q[3]
--operation mode is arithmetic

J1_safe_q[3]_carry_eqn = J1L6;
J1_safe_q[3]_lut_out = J1_safe_q[3] $ (J1_safe_q[3]_carry_eqn);
J1_safe_q[3] = DFFEAS(J1_safe_q[3]_lut_out, E1_cnt2, VCC, , , , , , );

--J1L8 is uart:inst|br_gen:u1|lpm_counter:ctr2_rtl_0|cntr_rm6:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

J1L8 = CARRY(!J1L6 # !J1_safe_q[3]);


--E1L21 is uart:inst|br_gen:u1|bclkx8~22
--operation mode is normal

E1L21 = sel[1] & E1L11 & J1_safe_q[3] # !E1L11 & J1_safe_q[2] # !sel[1] & E1L11;


--F1_bclkx8_dlayed is uart:inst|uart_receiver:u2|bclkx8_dlayed
--operation mode is normal

F1_bclkx8_dlayed_lut_out = E1L51;
F1_bclkx8_dlayed = DFFEAS(F1_bclkx8_dlayed_lut_out, clk, rst_n, , , , , , );


--F1_bclkx8_rising is uart:inst|uart_receiver:u2|bclkx8_rising
--operation mode is normal

F1_bclkx8_rising = !F1_bclkx8_dlayed & sel[2] & E1L41 # !sel[2] & E1L21;


--F1_ct1[2] is uart:inst|uart_receiver:u2|ct1[2]
--operation mode is normal

F1_ct1[2]_lut_out = !F1L21 & F1_ct1[2] $ (F1_ct1[1] & F1L1);
F1_ct1[2] = DFFEAS(F1_ct1[2]_lut_out, clk, rst_n, , , , , , );


--F1_ct1[1] is uart:inst|uart_receiver:u2|ct1[1]
--operation mode is normal

F1_ct1[1]_lut_out = !F1L21 & F1_ct1[1] $ (F1_ct1[0] & F1L22);
F1_ct1[1] = DFFEAS(F1_ct1[1]_lut_out, clk, rst_n, , , , , , );


--F1_ct1[0] is uart:inst|uart_receiver:u2|ct1[0]
--operation mode is normal

F1_ct1[0]_lut_out = !F1L21 & F1_ct1[0] $ F1L22;
F1_ct1[0] = DFFEAS(F1_ct1[0]_lut_out, clk, rst_n, , , , , , );


--F1L92 is uart:inst|uart_receiver:u2|ok_en~52
--operation mode is normal

F1L92 = F1_bclkx8_rising & F1_ct1[2] & F1_ct1[1] & F1_ct1[0];


--F1_state.recv_data is uart:inst|uart_receiver:u2|state.recv_data
--operation mode is normal

F1_state.recv_data_lut_out = F1L62 # F1_state.recv_data & F1L54 # !F1L92;
F1_state.recv_data = DFFEAS(F1_state.recv_data_lut_out, clk, rst_n, , , , , , );


--F1_ct2[2] is uart:inst|uart_receiver:u2|ct2[2]
--operation mode is normal

F1_ct2[2]_lut_out = F1L6;
F1_ct2[2] = DFFEAS(F1_ct2[2]_lut_out, clk, rst_n, , , , , , );


--F1_ct2[1] is uart:inst|uart_receiver:u2|ct2[1]
--operation mode is normal

F1_ct2[1]_lut_out = F1L4;
F1_ct2[1] = DFFEAS(F1_ct2[1]_lut_out, clk, rst_n, , , , , , );


--F1_ct2[0] is uart:inst|uart_receiver:u2|ct2[0]
--operation mode is normal

F1_ct2[0]_lut_out = F1L2;
F1_ct2[0] = DFFEAS(F1_ct2[0]_lut_out, clk, rst_n, , , , , , );


--F1_ct2[3] is uart:inst|uart_receiver:u2|ct2[3]
--operation mode is normal

F1_ct2[3]_lut_out = F1L8 & F1L54 # !F1_state.recv_data # !F1L92;
F1_ct2[3] = DFFEAS(F1_ct2[3]_lut_out, clk, rst_n, , , , , , );


--F1L54 is uart:inst|uart_receiver:u2|reduce_or~36
--operation mode is normal

F1L54 = F1_ct2[2] # F1_ct2[1] # F1_ct2[0] # !F1_ct2[3];


--F1L03 is uart:inst|uart_receiver:u2|ok_en~53
--operation mode is normal

F1L03 = F1L92 & F1_state.recv_data & rxd & !F1L54;


--G1L5 is uart:inst|uart_transmitter:u3|add~43
--operation mode is arithmetic

G1L5_carry_eqn = G1L4;
G1L5 = G1_bct[2] $ (!G1L5_carry_eqn);

--G1L6 is uart:inst|uart_transmitter:u3|add~43COUT
--operation mode is arithmetic

G1L6 = CARRY(G1_bct[2] & !G1L4);


--G1L3 is uart:inst|uart_transmitter:u3|add~42
--operation mode is arithmetic

G1L3_carry_eqn = G1L2;
G1L3 = G1_bct[1] $ (G1L3_carry_eqn);

--G1L4 is uart:inst|uart_transmitter:u3|add~42COUT
--operation mode is arithmetic

G1L4 = CARRY(!G1L2 # !G1_bct[1]);


--G1L7 is uart:inst|uart_transmitter:u3|add~44
--operation mode is normal

G1L7_carry_eqn = G1L6;
G1L7 = G1_bct[3] $ (G1L7_carry_eqn);


--G1L1 is uart:inst|uart_transmitter:u3|add~41
--operation mode is arithmetic

G1L1 = G1L41 $ G1_bct[0];

--G1L2 is uart:inst|uart_transmitter:u3|add~41COUT
--operation mode is arithmetic

G1L2 = CARRY(G1L41 & G1_bct[0]);


--G1_state.synch is uart:inst|uart_transmitter:u3|state.synch
--operation mode is normal

G1_state.synch_lut_out = G1L51 # G1_state.synch & G1_bclk_dlayed # !E1_ctr3[2];
G1_state.synch = DFFEAS(G1_state.synch_lut_out, clk, rst_n, , , , , , );


--E1L51 is uart:inst|br_gen:u1|bclkx8~29
--operation mode is normal

E1L51 = sel[2] & E1L41 # !sel[2] & E1L21;


--E1_ctr3[1] is uart:inst|br_gen:u1|ctr3[1]
--operation mode is normal

E1_ctr3[1]_lut_out = !E1_ctr3[1];
E1_ctr3[1] = DFFEAS(E1_ctr3[1]_lut_out, E1L51, VCC, , E1_ctr3[0], , , , );


--E1_ctr3[0] is uart:inst|br_gen:u1|ctr3[0]
--operation mode is normal

E1_ctr3[0]_lut_out = !E1_ctr3[0];
E1_ctr3[0] = DFFEAS(E1_ctr3[0]_lut_out, E1L51, VCC, , , , , , );


--E1L1 is uart:inst|br_gen:u1|add~90
--operation mode is normal

E1L1 = E1_ctr3[1] & E1_ctr3[0];


--G1_txd_startH_d1 is uart:inst|uart_transmitter:u3|txd_startH_d1
--operation mode is normal

G1_txd_startH_d1_lut_out = G1_txd_startH_d0;
G1_txd_startH_d1 = DFFEAS(G1_txd_startH_d1_lut_out, clk, VCC, , rst_n, , , , );


--G1_state.idle is uart:inst|uart_transmitter:u3|state.idle
--operation mode is normal

G1_state.idle_lut_out = G1L43 & G1_state.idle # !G1_txd_startH_d0 & G1_txd_startH_d1;
G1_state.idle = DFFEAS(G1_state.idle_lut_out, clk, rst_n, , , , , , );


--G1_txd_startH_d0 is uart:inst|uart_transmitter:u3|txd_startH_d0
--operation mode is normal

G1_txd_startH_d0_lut_out = txd_startH;
G1_txd_startH_d0 = DFFEAS(G1_txd_startH_d0_lut_out, clk, VCC, , rst_n, , , , );


--G1L51 is uart:inst|uart_transmitter:u3|loadTSR~31
--operation mode is normal

G1L51 = G1_txd_startH_d1 & !G1_state.idle & !G1_txd_startH_d0;


--G1L41 is uart:inst|uart_transmitter:u3|inc~36
--operation mode is normal

G1L41 = G1L71 & G1_state.tdata & E1_ctr3[2] & !G1_bclk_dlayed;


--G1_tsr[1] is uart:inst|uart_transmitter:u3|tsr[1]
--operation mode is normal

G1_tsr[1]_lut_out = G1L51 & F1_RDR[0] # !G1L51 & G1_tsr[2];
G1_tsr[1] = DFFEAS(G1_tsr[1]_lut_out, clk, rst_n, , G1L52, , , , );


--G1L23 is uart:inst|uart_transmitter:u3|tsr~829
--operation mode is normal

G1L23 = G1L41 & !G1_tsr[1] # !G1L41 & !G1_tsr[0];


--D1_sel[1] is scan:inst6|sel[1]
--operation mode is normal

D1_sel[1]_lut_out = !D1_sel[1];
D1_sel[1] = DFFEAS(D1_sel[1]_lut_out, K1_safe_q[13], rst_n, , D1_sel[0], , , , );


--D1_sel[0] is scan:inst6|sel[0]
--operation mode is normal

D1_sel[0]_lut_out = !D1_sel[0];
D1_sel[0] = DFFEAS(D1_sel[0]_lut_out, K1_safe_q[13], rst_n, , , , , , );


--K1_safe_q[13] is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|safe_q[13]
--operation mode is arithmetic

K1_safe_q[13]_carry_eqn = K1L62;
K1_safe_q[13]_lut_out = K1_safe_q[13] $ (K1_safe_q[13]_carry_eqn);
K1_safe_q[13] = DFFEAS(K1_safe_q[13]_lut_out, clk, !C1L1, , , , , , );

--K1L82 is clk_div:inst1|lpm_counter:cnt_rtl_1|cntr_b67:auto_generated|counter_cella13~COUT
--operation mode is arithmetic

K1L82 = CARRY(!K1L62 # !K1_safe_q[13]);