# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		uart_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:00:13  APRIL 16, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VHDL_FILE br_gen.vhd
set_global_assignment -name VHDL_FILE uart.vhd
set_global_assignment -name VHDL_FILE uart_receiver.vhd
set_global_assignment -name VHDL_FILE uart_transmitter.vhd
set_global_assignment -name BDF_FILE uart_test.bdf
set_global_assignment -name VHDL_FILE clk_div.vhd
set_global_assignment -name VHDL_FILE scan.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_18 -to clk
set_location_assignment PIN_131 -to rst_n
set_location_assignment PIN_49 -to rxd
set_location_assignment PIN_48 -to rxd_readyH
set_location_assignment PIN_139 -to sel[0]
set_location_assignment PIN_138 -to sel[1]
set_location_assignment PIN_4 -to sel[2]
set_location_assignment PIN_129 -to txd
set_location_assignment PIN_120 -to txd_doneH
set_location_assignment PIN_102 -to txd_startH
set_location_assignment PIN_44 -to seven_seg[0]
set_location_assignment PIN_50 -to seven_seg[1]
set_location_assignment PIN_134 -to seven_seg[3]
set_location_assignment PIN_140 -to seven_seg[4]
set_location_assignment PIN_45 -to seven_seg[6]
set_location_assignment PIN_125 -to seven_seg[7]
set_location_assignment PIN_137 -to dig1
set_location_assignment PIN_43 -to dig2
set_location_assignment PIN_42 -to dig3
set_location_assignment PIN_101 -to dig4

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY uart_test

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EPM1270T144C5

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL "1 ns"

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

set_global_assignment -name BDF_FILE Block1.bdf
set_global_assignment -name BDF_FILE uart.bdf