DDR_CLK - Quartus II Simulation Report File
-------------------------------------------------------------------------------

+-------------------------------------------------------------------------------------------------------------------------+
|Report Information                                                                                                       |
+------------------+------------------------------------------------------------------------------------------------------+
|Project           |D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\db\DDR_CLK.quartus_db|
|Simulator Settings|DDR_CLK                                                                                               |
|Quartus II Version|2.0 Build 204 03/26/2002 SP 1                                                                         |
+------------------+------------------------------------------------------------------------------------------------------+

Table of Contents
    Simulator Report
        Legal Notice
        Project Settings
            General Settings
        Results for "DDR_CLK" Simulator Settings
            Summary
            Simulator Settings
            Simulation Waveforms
            Messages
            Processing Time

+-----------------------------------------------------------------------------+
|Legal Notice                                                                 |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
|General Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option           |Setting            |
+-----------------+-------------------+
|Start date & time|06/20/2002 08:56:19|
|Main task        |Simulation         |
|Settings name    |DDR_CLK            |
|Simulation mode  |Functional         |
|Compiler Settings|DDR_CLK            |
+-----------------+-------------------+

+-----------------------------------------------------------------------------+
|Summary                                                                      |
+-----------------------------------------------------------------------------+
+---------------------+------------+
|Option               |Setting     |
+---------------------+------------+
|Simulation Start Time|0 ps        |
|Simulation End Time  |1.0 us      |
|Simulation Coverage  |        86 %|
+---------------------+------------+

+-----------------------------------------------------------------------------+
|Simulator Settings                                                           |
+-----------------------------------------------------------------------------+
+-----------------------------------------------------+--------------------------------------------------------------------------------------------+
|Option                                               |Setting                                                                                     |
+-----------------------------------------------------+--------------------------------------------------------------------------------------------+
|Simulation mode                                      |Functional                                                                                  |
|Simulator settings name                              |DDR_CLK                                                                                     |
|Start time                                           |0ns                                                                                         |
|Vector input source                                  |D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\DDR_CLK.vwf|
|Check outputs                                        |Off                                                                                         |
|Detect glitches                                      |Off                                                                                         |
|Glitch interval                                      |1ns                                                                                         |
|Report simulation coverage                           |On                                                                                          |
|Add pins automatically to simulation output waveforms|On                                                                                          |
|Estimate power consumption                           |Off                                                                                         |
|Detect setup and hold time violations                |Off                                                                                         |
+-----------------------------------------------------+--------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------+
|Simulation Waveforms                                                         |
+-----------------------------------------------------------------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.

+-----------------------------------------------------------------------------+
|Messages                                                                     |
+-----------------------------------------------------------------------------+
Info: Design DDR_CLK: Simulation was successful. 0 errors, 0 warnings

+-----------------------------------------------------------------------------+
|Processing Time                                                              |
+-----------------------------------------------------------------------------+
+---------------+------------+
|Module Name    |Elapsed Time|
+---------------+------------+
|Netlist Builder|00:00:01    |
|Simulator      |00:00:01    |
+---------------+------------+