?? clock.map.rpt
字號:
Analysis & Synthesis report for clock
Sun Mar 09 21:08:04 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Mar 09 21:08:04 2008 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name ; clock ;
; Top-level Entity Name ; reg ;
; Family ; FLEX10K ;
; Total logic elements ; 16 ;
; Total pins ; 33 ;
; Total memory bits ; 0 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------+----------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+----------------+---------------+
; Device ; EPF10K10LC84-3 ; ;
; Top-level entity name ; reg ; clock ;
; Family name ; FLEX10K ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+------------------------------------------------------------+----------------+---------------+
+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; reg.vhd ; yes ; User VHDL File ; E:/EDA/EDA_code/clock/reg.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource ; Usage ;
+---------------------------------+-----------+
; Total logic elements ; 16 ;
; Total combinational functions ; 0 ;
; -- Total 4-input functions ; 0 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 0 ;
; -- Total 1-input functions ; 0 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 16 ;
; I/O pins ; 33 ;
; Maximum fan-out node ; lock ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 48 ;
; Average fan-out ; 0.98 ;
+---------------------------------+-----------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |reg ; 16 (16) ; 16 ; 0 ; 33 ; 0 (0) ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; |reg ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 16 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/EDA_code/clock/clock.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sun Mar 09 21:08:02 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file count24.vhd
Info: Found design unit 1: count24-behave
Info: Found entity 1: count24
Info: Found 2 design units, including 1 entities, in source file clock.vhd
Info: Found design unit 1: clock-behave
Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file count10.vhd
Info: Found design unit 1: count10-behave
Info: Found entity 1: count10
Info: Found 2 design units, including 1 entities, in source file count6.vhd
Info: Found design unit 1: count6-behave
Info: Found entity 1: count6
Info: Found 2 design units, including 1 entities, in source file decoder7s.vhd
Info: Found design unit 1: decoder7s-behave
Info: Found entity 1: decoder7s
Info: Found 2 design units, including 1 entities, in source file scan.vhd
Info: Found design unit 1: scan-behave
Info: Found entity 1: scan
Info: Found 2 design units, including 1 entities, in source file count12.vhd
Info: Found design unit 1: count12-behave
Info: Found entity 1: count12
Info: Found 2 design units, including 1 entities, in source file timing.vhd
Info: Found design unit 1: timing-behave
Info: Found entity 1: timing
Info: Found 2 design units, including 1 entities, in source file division.vhd
Info: Found design unit 1: division-div1
Info: Found entity 1: division
Info: Found 2 design units, including 1 entities, in source file reg.vhd
Info: Found design unit 1: reg-behave
Info: Found entity 1: reg
Info: Elaborating entity "reg" for the top level hierarchy
Info: Implemented 49 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 16 output pins
Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Mar 09 21:08:04 2008
Info: Elapsed time: 00:00:03
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