?? division.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------
entity division is
generic (data : integer);
port(clk_in : in std_logic;
clk_out : out std_logic);
end entity division;
--------------------------------------------------------------
architecture div1 of division is
signal clk_outQ : std_logic ;
signal coutQ : integer;
begin
process(clk_in)
begin
if clk_in'event and clk_in='1' then
if coutQ /= (data/2 - 1) then
coutQ <= coutQ + 1;
else clk_outQ <= not clk_outQ;
coutQ <= 0;
end if;
end if;
end process;
clk_out <= clk_outQ;
end architecture div1;
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