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<p align="left"> 目 錄</p>
<img SRC="../../images/T.gif"><img SRC="../../images/nfolder.gif"><a href="y488941wz.pdf" target="mainFrame">文摘</a><br>
<img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y488941zye.pdf" target="mainFrame">英文文摘</a><br>
<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out1" CLASS="Outline" STYLE="cursor:hand"><a href="y4889410001.pdf" target="mainFrame">第一章緒論</a><br><%BOF%>
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<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y4889410002.pdf" target="mainFrame">1.1選題背景及其意義</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out12" CLASS="Outline" STYLE="cursor:hand"><a href="y4889410003.pdf" target="mainFrame">1.2專用集成電路(ASIC)高層次設(shè)計(jì)方法概述</a><br>
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<img SRC="../../images/I.gif"><img SRC="../../images/I.gif"><img SRC="../../images/H.gif"><img SRC="../../images/nfolder.gif"><a href="y4889410004.pdf" target="mainFrame">1.2.1高級(jí)綜合</a><br>
<img SRC="../../images/I.gif"><img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y4889410005.pdf" target="mainFrame">1.2.2 VHDL語言的產(chǎn)生與特點(diǎn)</a><br>
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<img SRC="../../images/I.gif"><img SRC="../../images/L.gif"><img SRC="../../images/nfolder.gif"><a href="y4889410006.pdf" target="mainFrame">1.3本文的主要工作及意義</a><br>
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<img SRC="../../images/H.gif"><img SRC="../../images/ofolder.gif" ID="Out2" CLASS="Outline" STYLE="cursor:hand"><a href="y4889410007.pdf" target="mainFrame">第二章基于VHDL系統(tǒng)的算法級(jí)行為描述</a><br>
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