?? count60_show.rpt
字號(hào):
- 1 - A 19 OR2 s ! 4 0 0 7 ~1649~1
- 7 - A 18 OR2 1 3 1 0 :1650
- 8 - A 18 OR2 s 1 3 0 1 ~1668~1
- 5 - A 18 OR2 1 3 1 0 :1668
- 4 - A 19 OR2 1 3 1 0 :1686
- 6 - A 18 OR2 1 3 1 0 :1704
- 6 - A 19 OR2 1 3 1 0 :1722
- 1 - A 18 OR2 1 3 1 0 :1740
- 2 - A 18 OR2 s ! 3 1 0 1 ~1742~1
- 3 - A 18 OR2 s 2 2 0 3 ~1742~2
- 7 - A 19 OR2 1 2 1 0 :1760
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl3\count60_show.rpt
count60_show
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 17/ 48( 35%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl3\count60_show.rpt
count60_show
** EQUATIONS **
inte0 : INPUT;
inte1 : INPUT;
inte2 : INPUT;
inte3 : INPUT;
inte4 : INPUT;
inte5 : INPUT;
-- Node name is 'a1'
-- Equation name is 'a1', type is output
a1 = _LC2_A22;
-- Node name is 'a2'
-- Equation name is 'a2', type is output
a2 = _LC7_A18;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC3_A20;
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = _LC5_A18;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC2_A23;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC4_A19;
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = _LC8_A20;
-- Node name is 'd2'
-- Equation name is 'd2', type is output
d2 = _LC6_A18;
-- Node name is 'e1'
-- Equation name is 'e1', type is output
e1 = _LC3_A23;
-- Node name is 'e2'
-- Equation name is 'e2', type is output
e2 = _LC6_A19;
-- Node name is 'f1'
-- Equation name is 'f1', type is output
f1 = _LC1_A20;
-- Node name is 'f2'
-- Equation name is 'f2', type is output
f2 = _LC1_A18;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = _LC5_A20;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = _LC7_A19;
-- Node name is '~309~1'
-- Equation name is '~309~1', location is LC3_A19, type is buried.
-- synthesized logic cell
_LC3_A19 = LCELL( _EQ001);
_EQ001 = !inte5 & _LC8_A19
# !inte2 & _LC8_A19
# !_LC5_A19 & _LC8_A19
# !inte2 & inte5
# inte5 & !_LC5_A19;
-- Node name is '~309~2'
-- Equation name is '~309~2', location is LC7_A14, type is buried.
-- synthesized logic cell
!_LC7_A14 = _LC7_A14~NOT;
_LC7_A14~NOT = LCELL( _EQ002);
_EQ002 = !inte3 & inte4
# inte2 & inte4
# inte2 & inte3
# inte3 & !inte4
# !inte2 & !inte3
# !inte2 & !inte4;
-- Node name is '~309~3'
-- Equation name is '~309~3', location is LC2_A14, type is buried.
-- synthesized logic cell
!_LC2_A14 = _LC2_A14~NOT;
_LC2_A14~NOT = LCELL( _EQ003);
_EQ003 = !inte1 & !inte5 & _LC3_A19
# inte1 & inte5 & _LC3_A19
# _LC3_A19 & !_LC7_A14;
-- Node name is '~349~1'
-- Equation name is '~349~1', location is LC5_A22, type is buried.
-- synthesized logic cell
!_LC5_A22 = _LC5_A22~NOT;
_LC5_A22~NOT = LCELL( _EQ004);
_EQ004 = !inte1
# inte2
# !inte5
# inte3;
-- Node name is '~390~1'
-- Equation name is '~390~1', location is LC5_A14, type is buried.
-- synthesized logic cell
_LC5_A14 = LCELL( _EQ005);
_EQ005 = inte1 & inte2 & !inte3 & inte5
# !inte1 & !inte2 & inte3 & !inte5;
-- Node name is '~471~1'
-- Equation name is '~471~1', location is LC6_A14, type is buried.
-- synthesized logic cell
_LC6_A14 = LCELL( _EQ006);
_EQ006 = inte1 & !inte2 & !inte3 & inte5
# inte1 & inte2 & inte3 & !inte5
# !inte1 & inte2 & inte3 & inte5
# !inte1 & inte2 & !inte3 & !inte5;
-- Node name is '~471~2'
-- Equation name is '~471~2', location is LC3_A14, type is buried.
-- synthesized logic cell
_LC3_A14 = LCELL( _EQ007);
_EQ007 = inte4 & _LC5_A14
# !inte4 & _LC6_A14;
-- Node name is ':471'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = LCELL( _EQ008);
_EQ008 = !inte0 & _LC3_A14;
-- Node name is ':555'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = LCELL( _EQ009);
_EQ009 = inte0
# !_LC2_A14 & !_LC3_A14;
-- Node name is '~579~1'
-- Equation name is '~579~1', location is LC5_A19, type is buried.
-- synthesized logic cell
!_LC5_A19 = _LC5_A19~NOT;
_LC5_A19~NOT = LCELL( _EQ010);
_EQ010 = !inte3
# !inte1
# inte4;
-- Node name is '~618~1'
-- Equation name is '~618~1', location is LC4_A23, type is buried.
-- synthesized logic cell
_LC4_A23 = LCELL( _EQ011);
_EQ011 = !inte1 & inte2 & !inte5 & !_LC4_A14;
-- Node name is '~633~1'
-- Equation name is '~633~1', location is LC5_A23, type is buried.
-- synthesized logic cell
_LC5_A23 = LCELL( _EQ012);
_EQ012 = !inte1 & !inte3 & inte5
# inte1 & inte3 & !inte4 & inte5
# inte1 & !inte3 & !inte5;
-- Node name is '~633~2'
-- Equation name is '~633~2', location is LC6_A23, type is buried.
-- synthesized logic cell
_LC6_A23 = LCELL( _EQ013);
_EQ013 = _LC4_A23
# inte2 & inte4 & _LC5_A23
# !inte2 & !inte4 & _LC5_A23;
-- Node name is '~673~1'
-- Equation name is '~673~1', location is LC4_A21, type is buried.
-- synthesized logic cell
_LC4_A21 = LCELL( _EQ014);
_EQ014 = inte5
# !inte4;
-- Node name is '~673~2'
-- Equation name is '~673~2', location is LC1_A21, type is buried.
-- synthesized logic cell
_LC1_A21 = LCELL( _EQ015);
_EQ015 = _LC4_A21
# !inte2;
-- Node name is ':714'
-- Equation name is '_LC3_A22', type is buried
!_LC3_A22 = _LC3_A22~NOT;
_LC3_A22~NOT = LCELL( _EQ016);
_EQ016 = !_LC5_A22 & _LC7_A22
# !inte4 & _LC7_A22
# !inte0;
-- Node name is '~795~1'
-- Equation name is '~795~1', location is LC6_A22, type is buried.
-- synthesized logic cell
_LC6_A22 = LCELL( _EQ017);
_EQ017 = inte1 & !inte3
# !inte3 & inte5
# inte1 & inte5
# !inte1 & inte3 & !inte5;
-- Node name is '~795~2'
-- Equation name is '~795~2', location is LC7_A22, type is buried.
-- synthesized logic cell
_LC7_A22 = LCELL( _EQ018);
_EQ018 = _LC6_A22
# inte4 & _LC4_A21
# inte2 & _LC4_A21
# !inte2 & inte4;
-- Node name is ':795'
-- Equation name is '_LC4_A22', type is buried
!_LC4_A22 = _LC4_A22~NOT;
_LC4_A22~NOT = LCELL( _EQ019);
_EQ019 = !_LC5_A22 & _LC7_A22
# !inte4 & _LC7_A22
# inte0;
-- Node name is ':796'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = LCELL( _EQ020);
_EQ020 = !_LC3_A22 & _LC8_A22
# _LC1_A23 & !_LC3_A22
# _LC4_A22;
-- Node name is '~826~1'
-- Equation name is '~826~1', location is LC6_A20, type is buried.
-- synthesized logic cell
_LC6_A20 = LCELL( _EQ021);
_EQ021 = inte0 & !_LC3_A14
# !_LC2_A14 & !_LC3_A14
# !inte0 & !_LC2_A14
# _LC1_A23;
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