library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity selectwave is
port(clk:in std_logic;
     sel:in std_logic_vector(1 downto 0);
     sin_data:in std_logic_vector(7 downto 0);
     delta_data:in std_logic_vector(7 downto 0);
     juchi_data:in std_logic_vector(7 downto 0);
     fang_data:in std_logic_vector(7 downto 0);
     data_out:out std_logic_vector(7 downto 0));
end ;

architecture sel of selectwave is
begin

    with sel select
    data_out<=delta_data when "00",
               sin_data when "01",
               juchi_data when "10",
              fang_data  when "11";

end;