|dds
output[0] <= selectwave:inst11.data_out[0]
output[1] <= selectwave:inst11.data_out[1]
output[2] <= selectwave:inst11.data_out[2]
output[3] <= selectwave:inst11.data_out[3]
output[4] <= selectwave:inst11.data_out[4]
output[5] <= selectwave:inst11.data_out[5]
output[6] <= selectwave:inst11.data_out[6]
output[7] <= selectwave:inst11.data_out[7]
gclock => frediv:inst13.clk
fcw[0] => add_fcw:inst.fcw[0]
fcw[1] => add_fcw:inst.fcw[1]
fcw[2] => add_fcw:inst.fcw[2]
fcw[3] => add_fcw:inst.fcw[3]
fcw[4] => add_fcw:inst.fcw[4]
fcw[5] => add_fcw:inst.fcw[5]
fcw[6] => add_fcw:inst.fcw[6]
fcw[7] => add_fcw:inst.fcw[7]
pcw[0] => add_pcw:inst1.pcw[0]
pcw[1] => add_pcw:inst1.pcw[1]
pcw[2] => add_pcw:inst1.pcw[2]
pcw[3] => add_pcw:inst1.pcw[3]
pcw[4] => add_pcw:inst1.pcw[4]
pcw[5] => add_pcw:inst1.pcw[5]
pcw[6] => add_pcw:inst1.pcw[6]
pcw[7] => add_pcw:inst1.pcw[7]
sel[0] => selectwave:inst11.sel[0]
sel[1] => selectwave:inst11.sel[1]


|dds|selectwave:inst11
clk => ~NO_FANOUT~
sel[0] => Mux0.IN1
sel[0] => Mux1.IN1
sel[0] => Mux2.IN1
sel[0] => Mux3.IN1
sel[0] => Mux4.IN1
sel[0] => Mux5.IN1
sel[0] => Mux6.IN1
sel[0] => Mux7.IN1
sel[1] => Mux0.IN0
sel[1] => Mux1.IN0
sel[1] => Mux2.IN0
sel[1] => Mux3.IN0
sel[1] => Mux4.IN0
sel[1] => Mux5.IN0
sel[1] => Mux6.IN0
sel[1] => Mux7.IN0
sin_data[0] => Mux7.IN2
sin_data[1] => Mux6.IN2
sin_data[2] => Mux5.IN2
sin_data[3] => Mux4.IN2
sin_data[4] => Mux3.IN2
sin_data[5] => Mux2.IN2
sin_data[6] => Mux1.IN2
sin_data[7] => Mux0.IN2
delta_data[0] => Mux7.IN3
delta_data[1] => Mux6.IN3
delta_data[2] => Mux5.IN3
delta_data[3] => Mux4.IN3
delta_data[4] => Mux3.IN3
delta_data[5] => Mux2.IN3
delta_data[6] => Mux1.IN3
delta_data[7] => Mux0.IN3
juchi_data[0] => Mux7.IN4
juchi_data[1] => Mux6.IN4
juchi_data[2] => Mux5.IN4
juchi_data[3] => Mux4.IN4
juchi_data[4] => Mux3.IN4
juchi_data[5] => Mux2.IN4
juchi_data[6] => Mux1.IN4
juchi_data[7] => Mux0.IN4
fang_data[0] => Mux7.IN5
fang_data[1] => Mux6.IN5
fang_data[2] => Mux5.IN5
fang_data[3] => Mux4.IN5
fang_data[4] => Mux3.IN5
fang_data[5] => Mux2.IN5
fang_data[6] => Mux1.IN5
fang_data[7] => Mux0.IN5
data_out[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|dds|frediv:inst14
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => tmpclk.CLK
clkout <= tmpclk.DB_MAX_OUTPUT_PORT_TYPE


|dds|frediv:inst13
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => tmpclk.CLK
clkout <= tmpclk.DB_MAX_OUTPUT_PORT_TYPE


|dds|delta:inst6
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|delta:inst6|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_hq31:auto_generated.address_a[0]
address_a[1] => altsyncram_hq31:auto_generated.address_a[1]
address_a[2] => altsyncram_hq31:auto_generated.address_a[2]
address_a[3] => altsyncram_hq31:auto_generated.address_a[3]
address_a[4] => altsyncram_hq31:auto_generated.address_a[4]
address_a[5] => altsyncram_hq31:auto_generated.address_a[5]
address_a[6] => altsyncram_hq31:auto_generated.address_a[6]
address_a[7] => altsyncram_hq31:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hq31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hq31:auto_generated.q_a[0]
q_a[1] <= altsyncram_hq31:auto_generated.q_a[1]
q_a[2] <= altsyncram_hq31:auto_generated.q_a[2]
q_a[3] <= altsyncram_hq31:auto_generated.q_a[3]
q_a[4] <= altsyncram_hq31:auto_generated.q_a[4]
q_a[5] <= altsyncram_hq31:auto_generated.q_a[5]
q_a[6] <= altsyncram_hq31:auto_generated.q_a[6]
q_a[7] <= altsyncram_hq31:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|delta:inst6|altsyncram:altsyncram_component|altsyncram_hq31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|dds|delta_address:inst7
clk => addout[0]~reg0.CLK
clk => addout[1]~reg0.CLK
clk => addout[2]~reg0.CLK
clk => addout[3]~reg0.CLK
clk => addout[4]~reg0.CLK
clk => addout[5]~reg0.CLK
clk => addout[6]~reg0.CLK
clk => addout[7]~reg0.CLK
addin[0] => addout~7.DATAA
addin[0] => addout~7.DATAB
addin[1] => addout~6.DATAA
addin[1] => addout~6.DATAB
addin[2] => addout~5.DATAA
addin[2] => addout~5.DATAB
addin[3] => addout~4.DATAA
addin[3] => addout~4.DATAB
addin[4] => addout~3.DATAA
addin[4] => addout~3.DATAB
addin[5] => addout~2.DATAA
addin[5] => addout~2.DATAB
addin[6] => addout~1.DATAA
addin[6] => addout~1.DATAB
addin[7] => addout~0.DATAA
addin[7] => addout~0.DATAB
addin[8] => addout~0.OUTPUTSELECT
addin[8] => addout~1.OUTPUTSELECT
addin[8] => addout~2.OUTPUTSELECT
addin[8] => addout~3.OUTPUTSELECT
addin[8] => addout~4.OUTPUTSELECT
addin[8] => addout~5.OUTPUTSELECT
addin[8] => addout~6.OUTPUTSELECT
addin[8] => addout~7.OUTPUTSELECT
addin[9] => ~NO_FANOUT~
addout[0] <= addout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[1] <= addout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[2] <= addout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[3] <= addout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[4] <= addout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[5] <= addout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[6] <= addout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[7] <= addout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|add_pcw:inst1
clr => address[0]~reg0.ACLR
clr => address[1]~reg0.ACLR
clr => address[2]~reg0.ACLR
clr => address[3]~reg0.ACLR
clr => address[4]~reg0.ACLR
clr => address[5]~reg0.ACLR
clr => address[6]~reg0.ACLR
clr => address[7]~reg0.ACLR
clr => address[8]~reg0.ACLR
clr => address[9]~reg0.ACLR
clk => address[0]~reg0.CLK
clk => address[1]~reg0.CLK
clk => address[2]~reg0.CLK
clk => address[3]~reg0.CLK
clk => address[4]~reg0.CLK
clk => address[5]~reg0.CLK
clk => address[6]~reg0.CLK
clk => address[7]~reg0.CLK
clk => address[8]~reg0.CLK
clk => address[9]~reg0.CLK
pcw[0] => Add0.IN10
pcw[1] => Add0.IN9
pcw[2] => Add0.IN8
pcw[3] => Add0.IN7
pcw[4] => Add0.IN6
pcw[5] => Add0.IN5
pcw[6] => Add0.IN4
pcw[7] => Add0.IN3
data_in[0] => Add0.IN20
data_in[1] => Add0.IN19
data_in[2] => Add0.IN18
data_in[3] => Add0.IN17
data_in[4] => Add0.IN16
data_in[5] => Add0.IN15
data_in[6] => Add0.IN14
data_in[7] => Add0.IN13
data_in[8] => Add0.IN12
data_in[9] => Add0.IN11
address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[5] <= address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[6] <= address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[7] <= address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[8] <= address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[9] <= address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|add_fcw:inst
clr => tmp[0].ACLR
clr => tmp[1].ACLR
clr => tmp[2].ACLR
clr => tmp[3].ACLR
clr => tmp[4].ACLR
clr => tmp[5].ACLR
clr => tmp[6].ACLR
clr => tmp[7].ACLR
clr => tmp[8].ACLR
clr => tmp[9].ACLR
clr => sum[0]~reg0.ACLR
clr => sum[1]~reg0.ACLR
clr => sum[2]~reg0.ACLR
clr => sum[3]~reg0.ACLR
clr => sum[4]~reg0.ACLR
clr => sum[5]~reg0.ACLR
clr => sum[6]~reg0.ACLR
clr => sum[7]~reg0.ACLR
clr => sum[8]~reg0.ACLR
clr => sum[9]~reg0.ACLR
clk => tmp[0].CLK
clk => tmp[1].CLK
clk => tmp[2].CLK
clk => tmp[3].CLK
clk => tmp[4].CLK
clk => tmp[5].CLK
clk => tmp[6].CLK
clk => tmp[7].CLK
clk => tmp[8].CLK
clk => tmp[9].CLK
clk => sum[0]~reg0.CLK
clk => sum[1]~reg0.CLK
clk => sum[2]~reg0.CLK
clk => sum[3]~reg0.CLK
clk => sum[4]~reg0.CLK
clk => sum[5]~reg0.CLK
clk => sum[6]~reg0.CLK
clk => sum[7]~reg0.CLK
clk => sum[8]~reg0.CLK
clk => sum[9]~reg0.CLK
fcw[0] => Add0.IN10
fcw[1] => Add0.IN9
fcw[2] => Add0.IN8
fcw[3] => Add0.IN7
fcw[4] => Add0.IN6
fcw[5] => Add0.IN5
fcw[6] => Add0.IN4
fcw[7] => Add0.IN3
sum[0] <= sum[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[1] <= sum[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[2] <= sum[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[3] <= sum[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[4] <= sum[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[5] <= sum[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[6] <= sum[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[7] <= sum[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[8] <= sum[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sum[9] <= sum[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|fangbo:inst10
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => counter[4].CLK
clk => counter[5].CLK
clk => counter[6].CLK
clk => counter[7].CLK
clk => counter[8].CLK
data_out[0] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE