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Chip NAND2-1

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Summary Information:

--------------------

Type: Initial implementation

Source: up to date

Status: 0 errors, 0 warnings, 0 messages



Target Information:

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Vendor: Altera

Family: MAX7000

Device: AUTO

Speed: FASTEST



Chip Parameters:

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Optimize for: Speed

Optimization effort: High

Frequency: 50 MHz

Is module: No

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

NAND2: defined in E:\HJB\VHDL\nand2.vhd



Primitive reference count:

--------------------------



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00     -1.00     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00      -1.00     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

a                      0.00      -1.00     (O)                  

b                      0.00      -1.00     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

Y                      0.00      -1.00     (I)