==================

Chip INV-Optimized

==================



Summary Information:

--------------------

Type: Optimized implementation

Source: INV, out-of-date

Status: 0 errors, 0 warnings, 0 messages

Export: not exported since last optimization



Target Information:

-------------------

Vendor: Altera

Family: MAX7000

Device: AUTO

Speed: FASTEST



Chip Parameters:

----------------

Optimize for: Speed

Optimization effort: High

Frequency: 50 MHz

Is module: No

Keep io pads: No

Number of flip-flops: 0

Number of latches: 0



Chip Design Hierarchy:

----------------------

INV: defined in E:\vhdl_tools\100Examples\TEMP\NAND2.vhd



Primitive reference count:

--------------------------

INV           1



Clocks:

-------

                           Required  Estimated                       

Period   Rise     Fall     Freq      Freq       Signal               

(ns)     (ns)     (ns)     (MHz)     (MHz)                           

...............................................................

 20        0       10       50.00     -1.00     default              



Timing Groups:

--------------

                                                              

                                                              

Name                 Description                              

............................................................

(I)                  Input ports                              

(O)                  Output ports                             



Timing Path Groups:

-------------------

                                          Required   Estimated  

                                          Delay      Delay      

From                 To                   (ns)       (ns)       

............................................................

(I)                  (O)                    1.00       0.50     



Input Port Timing:

------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       To-Group             

............................................................

A_IN                   0.50       0.50     (O)                  



Output Port Timing:

-------------------

                     Required   Estimated                       

Port                 Delay      Slack                           

Name                 (ns)       (ns)       From-Group           

............................................................

A_OUT                  1.00       0.50     (I)                  



Critical Path Timing:

---------------------

           Arrival    Required                                

Cell       Time       Time       Fanout                       

Type       (ns)       (ns)       Count   Pin-Name             

.........................................................

port         0.50       1.00       0     /INV-Optimized/A_OUT 

INV          0.50       1.00       0     /INV-Optimized/C5/A_O

INV          0.00       0.50       1     /INV-Optimized/C5/A_I

port         0.00       0.50       1     /INV-Optimized/A_IN