?? d.fit.rpt
字號:
Fitter report for d
Thu May 15 21:32:20 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. I/O Bank Usage
9. All Package Pins
10. Output Pin Default Load For Reported TCO
11. Fitter Resource Utilization by Entity
12. Delay Chain Summary
13. Pad To Core Delay Chain Fanout
14. Control Signals
15. Non-Global High Fan-Out Signals
16. Interconnect Usage Summary
17. LAB Logic Elements
18. LAB-wide Signals
19. LAB Signals Sourced
20. LAB Signals Sourced Out
21. LAB Distinct Inputs
22. Fitter Device Options
23. Advanced Data - General
24. Advanced Data - Placement Preparation
25. Advanced Data - Placement
26. Advanced Data - Routing
27. Fitter Messages
28. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------+
; Fitter Status ; Successful - Thu May 15 21:32:20 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name ; d ;
; Top-level Entity Name ; d ;
; Family ; Cyclone ;
; Device ; EP1C3T144C8 ;
; Timing Models ; Final ;
; Total logic elements ; 1 / 2,910 ( < 1 % ) ;
; Total pins ; 3 / 104 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 59,904 ( 0 % ) ;
; Total PLLs ; 0 / 1 ( 0 % ) ;
+-----------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1C3T144C8 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Calvin/桌面/111/d.pin.
+-------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+---------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------+
; Total logic elements ; 1 / 2,910 ( < 1 % ) ;
; -- Combinational with no register ; 0 ;
; -- Register only ; 1 ;
; -- Combinational with a register ; 0 ;
; ; ;
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