/* * Copyright (c) 2000-2004 by David Brownell *  * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */#include <linux/config.h>#ifdef CONFIG_USB_DEBUG	#define DEBUG#else	#undef DEBUG#endif#include <rtdm/rtdm_driver.h>#include <linux/pci.h>#include <linux/reboot.h>#include "../../usb_rtdm.h"#include "../../core/hcd.h"/*-------------------------------------------------------------------------*//* * EHCI hc_driver implementation ... experimental, incomplete. * Based on the final 1.0 register interface specification. * * USB 2.0 shows up in upcoming www.pcmcia.org technology. * First was PCMCIA, like ISA; then CardBus, which is PCI. * Next comes "CardBay", using USB 2.0 signals. * * Contains additional contributions by Brad Hards, Rory Bolt, and others. * Special thanks to Intel and VIA for providing host controllers to * test this driver on, and Cypress (including In-System Design) for * providing early devices for those host controllers to talk to! * * HISTORY: * * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, *	<sojkam@centrum.cz>, updates by DB). * * 2002-11-29	Correct handling for hw async_next register. * 2002-08-06	Handling for bulk and interrupt transfers is mostly shared; *	only scheduling is different, no arbitrary limitations. * 2002-07-25	Sanity check PCI reads, mostly for better cardbus support, * 	clean up HC run state handshaking. * 2002-05-24	Preliminary FS/LS interrupts, using scheduling shortcuts * 2002-05-11	Clear TT errors for FS/LS ctrl/bulk.  Fill in some other *	missing pieces:  enabling 64bit dma, handoff from BIOS/SMM. * 2002-05-07	Some error path cleanups to report better errors; wmb(); *	use non-CVS version id; better iso bandwidth claim. * 2002-04-19	Control/bulk/interrupt submit no longer uses giveback() on *	errors in submit path.  Bugfixes to interrupt scheduling/processing. * 2002-03-05	Initial high-speed ISO support; reduce ITD memory; shift *	more checking to generic hcd framework (db).  Make it work with *	Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). * 2002-01-14	Minor cleanup; version synch. * 2002-01-08	Fix roothub handoff of FS/LS to companion controllers. * 2002-01-04	Control/Bulk queuing behaves. * * 2001-12-12	Initial patch version for Linux 2.5.1 kernel. * 2001-June	Works with usb-storage and NEC EHCI on 2.4 * (C) Copyright 2006 Gerard Harkema (Adapted for xenomai RTDM) G.A.Harkema@tue.nl */#define DRIVER_VERSION "01 july 2006"#define DRIVER_AUTHOR "David Brownell, Gerard Harkema"#define DRIVER_DESC "USB 2.0 'RTDM' Enhanced Host Controller (EHCI) Driver"static const char	hcd_name [] = "rtdm_ehci_hcd";#undef EHCI_VERBOSE_DEBUG#undef EHCI_URB_TRACE#define EHCI_VERBOSE_DEBUG#define EHCI_URB_TRACE#define DEBUG#ifdef DEBUG#define EHCI_STATS#endif/* magic numbers that can affect system performance */#define	EHCI_TUNE_CERR		3	/* 0-3 qtd retries; 0 == don't stop */#define	EHCI_TUNE_RL_HS		4	/* nak throttle; see 4.9 */#define	EHCI_TUNE_RL_TT		0#define	EHCI_TUNE_MULT_HS	1	/* 1-3 transactions/uframe; 4.10.3 */#define	EHCI_TUNE_MULT_TT	1#define	EHCI_TUNE_FLS		2	/* (small) 256 frame schedule */#define EHCI_IAA_JIFFIES	(HZ/100)	/* arbitrary; ~10 msec */#define EHCI_IO_JIFFIES		(HZ/10)		/* io watchdog > irq_thresh */#define EHCI_ASYNC_JIFFIES	(HZ/20)		/* async idle timeout */#define EHCI_SHRINK_JIFFIES	(HZ/200)	/* async qh unlink delay *//* Initial IRQ latency:  faster than hw default */static int log2_irq_thresh = 0;		// 0 to 6module_param (log2_irq_thresh, int, S_IRUGO);MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");/* initial park setting:  slower than hw default */static unsigned park = 0;module_param (park, uint, S_IRUGO);MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");#define	INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)/*-------------------------------------------------------------------------*/#include "ehci.h"#include "ehci-dbg.c"/*-------------------------------------------------------------------------*//* * handshake - spin reading hc until handshake completes or fails * @ptr: address of hc register to be read * @mask: bits to look at in result of read * @done: value of those bits when handshake succeeds * @usec: timeout in microseconds * * Returns negative errno, or zero on success * * Success happens when the "mask" bits have the specified value (hardware * handshake done).  There are two failure modes:  "usec" have passed (major * hardware flakeout), or the register reads as all-ones (hardware removed). * * That last failure should_only happen in cases like physical cardbus eject * before driver shutdown. But it also seems to be caused by bugs in cardbus * bridge shutdown:  shutting down the bridge before the devices using it. */static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec){	u32	result;	do {		result = readl (ptr);		if (result == ~(u32)0)		/* card removed */			return -ENODEV;		result &= mask;		if (result == done)			return 0;		udelay (1);		usec--;	} while (usec > 0);	return -ETIMEDOUT;}/* force HC to halt state from unknown (EHCI spec section 2.3) */static int ehci_halt (struct ehci_hcd *ehci){	u32	temp = readl (&ehci->regs->status);	if ((temp & STS_HALT) != 0)		return 0;	temp = readl (&ehci->regs->command);	temp &= ~CMD_RUN;	writel (temp, &ehci->regs->command);	return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);}/* put TDI/ARC silicon into EHCI mode */static void tdi_reset (struct ehci_hcd *ehci){	u32 __iomem	*reg_ptr;	u32		tmp;	reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68);	tmp = readl (reg_ptr);	tmp |= 0x3;	writel (tmp, reg_ptr);}/* reset a non-running (STS_HALT == 1) controller */static int ehci_reset (struct ehci_hcd *ehci){	int	retval;	u32	command = readl (&ehci->regs->command);	command |= CMD_RESET;	dbg_cmd (ehci, "reset", command);	writel (command, &ehci->regs->command);	ehci_to_hcd(ehci)->state = HC_STATE_HALT;	ehci->next_statechange = jiffies;	retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);	if (retval)		return retval;	if (ehci_is_TDI(ehci))		tdi_reset (ehci);	return retval;}/* idle the controller (from running) */static void ehci_quiesce (struct ehci_hcd *ehci){	u32	temp;#ifdef DEBUG	if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))		BUG ();#endif	/* wait for any schedule enables/disables to take effect */	temp = readl (&ehci->regs->command) << 10;	temp &= STS_ASS | STS_PSS;	if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,				temp, 16 * 125) != 0) {		ehci_to_hcd(ehci)->state = HC_STATE_HALT;		return;	}	/* then disable anything that's still active */	temp = readl (&ehci->regs->command);	temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);	writel (temp, &ehci->regs->command);	/* hardware can take 16 microframes to turn off ... */	if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,				0, 16 * 125) != 0) {		ehci_to_hcd(ehci)->state = HC_STATE_HALT;		return;	}}/*-------------------------------------------------------------------------*/static void ehci_work(struct ehci_hcd *ehci);#include "ehci-hub.c"#include "ehci-mem.c"#include "ehci-q.c"#include "ehci-sched.c"/*-------------------------------------------------------------------------*/static void ehci_watchdog (unsigned long param){	struct ehci_hcd		*ehci = (struct ehci_hcd *) param;	unsigned long		context;	rtdm_lock_get_irqsave(&ehci->rt_lock, context);	/* lost IAA irqs wedge things badly; seen with a vt8235 */	if (ehci->reclaim) {		u32		status = readl (&ehci->regs->status);		if (status & STS_IAA) {			ehci_vdbg (ehci, "lost IAA\n");			COUNT (ehci->stats.lost_iaa);			writel (STS_IAA, &ehci->regs->status);			ehci->reclaim_ready = 1;		}	} 	/* stop async processing after it's idled a bit */	if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 		start_unlink_async (ehci, ehci->async);	/* ehci could run by timer, without IRQs ... */	ehci_work (ehci);	rtdm_lock_put_irqrestore(&ehci->rt_lock, context);}#ifdef	CONFIG_PCI/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/... * off the controller (maybe it can boot from highspeed USB disks). */static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap){	struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);	/* always say Linux will own the hardware */	pci_write_config_byte(pdev, where + 3, 1);	/* maybe wait a while for BIOS to respond */	if (cap & (1 << 16)) {		int msec = 5000;		do {			if(rtdm_in_rt_context())				rtdm_task_sleep(1000000 * 10);			else				msleep(10);			msec -= 10;			pci_read_config_dword(pdev, where, &cap);		} while ((cap & (1 << 16)) && msec);		if (cap & (1 << 16)) {			ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",				where, cap);			// some BIOS versions seem buggy...			// return 1;			ehci_warn (ehci, "continuing after BIOS bug...\n");			/* disable all SMIs, and clear "BIOS owns" flag */			pci_write_config_dword(pdev, where + 4, 0);			pci_write_config_byte(pdev, where + 2, 0);		} else			ehci_dbg(ehci, "BIOS handoff succeeded\n");	}	return 0;}#endifstatic intehci_reboot (struct notifier_block *self, unsigned long code, void *null){	struct ehci_hcd		*ehci;	ehci = container_of (self, struct ehci_hcd, reboot_notifier);	/* make BIOS/etc use companion controller during reboot */	writel (0, &ehci->regs->configured_flag);	return 0;}static void ehci_port_power (struct ehci_hcd *ehci, int is_on){	unsigned port;	if (!HCS_PPC (ehci->hcs_params))		return;	ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");	for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )		(void) ehci_hub_control(ehci_to_hcd(ehci),				is_on ? SetPortFeature : ClearPortFeature,				USB_PORT_FEAT_POWER,				port--, NULL, 0);	if(rtdm_in_rt_context())		rtdm_task_sleep(1000000 * 20);	else		msleep(20);}/* called by khubd or root hub init threads */static int ehci_hc_reset (struct usb_hcd *hcd){	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);	u32			temp;	unsigned		count = 256/4;	spin_lock_init (&ehci->rt_lock);	ehci->caps = hcd->regs;	ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));	dbg_hcs_params (ehci, "reset");	dbg_hcc_params (ehci, "reset");	/* cache this readonly data; minimize chip reads */	ehci->hcs_params = readl (&ehci->caps->hcs_params);#ifdef	CONFIG_PCI	if (hcd->self.controller->bus == &pci_bus_type) {		struct pci_dev	*pdev = to_pci_dev(hcd->self.controller);		switch (pdev->vendor) {		case PCI_VENDOR_ID_TDI:			if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {				ehci->is_tdi_rh_tt = 1;				tdi_reset (ehci);			}			break;		case PCI_VENDOR_ID_AMD:			/* AMD8111 EHCI doesn't work, according to AMD errata */			if (pdev->device == 0x7463) {				ehci_info (ehci, "ignoring AMD8111 (errata)\n");				return -EIO;			}			break;		case PCI_VENDOR_ID_NVIDIA:			/* NVidia reports that certain chips don't handle			 * QH, ITD, or SITD addresses above 2GB.  (But TD,			 * data buffer, and periodic schedule are normal.)			 */			switch (pdev->device) {			case 0x003c:	/* MCP04 */			case 0x005b:	/* CK804 */			case 0x00d8:	/* CK8 */			case 0x00e8:	/* CK8S */				if (pci_set_consistent_dma_mask(pdev,							DMA_31BIT_MASK) < 0)					ehci_warn (ehci, "can't enable NVidia "						"workaround for >2GB RAM\n");				break;			}			break;		}		/* optional debug port, normally in the first BAR */