LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
?NTITY EX10 IS
PORT (
	clk1Hz : IN STD_LOGIC; 
	uclk : IN STD_LOGIC; 
	led0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	led1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	led2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
led3 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	p_cnt_en : OUT STD_LOGIC; -- IO01
	p_rst_cnt: OUT STD_LOGIC; -- IO00
	p_load : OUT STD_LOGIC -- IO02
);
END EX10; 
ARCHITECTURE behv OF EX10 IS
COMPONENT cnt10
	PORT (
		clk : IN STD_LOGIC;
		rst : IN STD_LOGIC;
		ena : IN STD_LOGIC;
		outy: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		cout: OUT STD_LOGIC
);
END COMPONENT;
?
COMPONENT reg4b
	PORT (
		load: IN STD_LOGIC;
		din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		dout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;

COMPONENT testctl
	PORT (
		clkk : IN STD_LOGIC;
		cnt_en : OUT STD_LOGIC;
		rst_cnt: OUT STD_LOGIC;
		load : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL cnt_en : STD_LOGIC;
	SIGNAL rst_cnt : STD_LOGIC;
	SIGNAL load : STD_LOGIC;
	SIGNAL dout0, dout1, dout2, dout3:     
                            STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL   
           cout0, cout1, cout2, cout3: STD_LOGIC; 
BEGIN
	p_cnt_en <= cnt_en ;
	p_rst_cnt <= rst_cnt;
	p_load <= load ;
u_testctl: testctl PORT MAP (
	clkk => clk1Hz ,
	cnt_en => cnt_en ,
	rst_cnt => rst_cnt,
	load => load
);
u_cnt10_0: cnt10 PORT MAP (
	clk => uclk ,
	rst => rst_cnt,
	ena => cnt_en ,
	outy => dout0 ,
	cout => cout0
);

u_cnt10_1: cnt10 PORT MAP (
	clk => cout0 ,
	rst => rst_cnt,
	ena => cnt_en ,
	outy => dout1 ,
	cout => cout1
);
u_cnt10_2: cnt10 PORT MAP (
	clk => cout1 ,
	rst => rst_cnt,
	ena => cnt_en ,
	outy => dout2 ,
	cout => cout2
);

u_cnt10_3: cnt10 PORT MAP (
	clk => cout2 ,
	rst => rst_cnt,
	ena => cnt_en ,
	outy => dout3 ,
	cout => cout3
);
u_reg4b_0: reg4b PORT MAP (
	load => load ,
	din => dout0,
	dout => led0
);
u_reg4b_1: reg4b PORT MAP (
	load => load ,
	din => dout1,
	dout => led1
);

u_cnt10_3: cnt10 PORT MAP (
	clk => cout2 ,
	rst => rst_cnt,
	ena => cnt_en ,
	outy => dout3 ,
	cout => cout3
);
u_reg4b_0: reg4b PORT MAP (
	load => load ,
	din => dout0,
	dout => led0
);
u_reg4b_1: reg4b PORT MAP (
	load => load ,
	din => dout1,
	dout => led1
);

u_reg4b_2: reg4b PORT MAP (
	load => load ,
	din => dout2,
	dout => led2
);
u_reg4b_3: reg4b PORT MAP (
	load => load ,
	din => dout3,
	dout => led3
);
END behv;

--TESTCTL.VHD程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
?
ENTITY testctl IS
PORT (
	clkk : IN STD_LOGIC;
	cnt_en : OUT STD_LOGIC;
	rst_cnt: OUT STD_LOGIC;
	load : OUT STD_LOGIC
);
END testctl;
?
ARCHITECTURE behv OF testctl IS
	SIGNAL div2clk: STD_LOGIC;
BEGIN 
--TESTCTL.VHD程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
?
ENTITY testctl IS
PORT (
	clkk : IN STD_LOGIC;
	cnt_en : OUT STD_LOGIC;
	rst_cnt: OUT STD_LOGIC;
	load : OUT STD_LOGIC
);
END testctl;
?
ARCHITECTURE behv OF testctl IS
	SIGNAL div2clk: STD_LOGIC;
BEGIN 
BEGIN
	IF clkk'EVENT AND clkk = '1' THEN
		div2clk <= NOT div2clk;
	END IF;
END PROCESS;
?
PROCESS(clkk, div2clk)
BEGIN
	IF clkk = '0' AND div2clk = '0' THEN
		rst_cnt <= '1';
	ELSE
		rst_cnt <= '0';
	END IF;
	load <= NOT div2clk;
	cnt_en <= div2clk;
END PROCESS;
END behv;

--CNT10.VHD程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
?
ENTITY cnt10 IS
PORT (
	clk : IN STD_LOGIC;
	rst : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	outy: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	cout: OUT STD_LOGIC
);
END cnt10;

ARCHITECTURE behv OF cnt10 IS
	SIGNAL cqi: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk, rst, ena)
BEGIN
	IF rst = '1' THEN
cqi <= "0000";
		cout <= '0';
	ELSIF clk'EVENT AND clk = '1' THEN
		IF ena = '1' THEN
			IF cqi = "1001" THEN
				cqi <= "0000";
				cout <= '1';
			ELS
				cqi <= cqi + 1;
				cout <= '0';
			END IF;
		END IF;
	END IF;
	outy <= cqi;
END PROCESS;
END behv;

--REG4B.VHD程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
?ENTITY reg4b IS
PORT (
	load: IN STD_LOGIC;
	din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	dout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END reg4b;
?
ARCHITECTURE behv OF reg4b IS
BEGIN
PROCESS(load)
BEGIN
	IF load 'EVENT AND load = '1' THEN
		dout <= din;
	END IF;
END PROCESS;
END behv;