{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 13 23:38:52 2008 " "Info: Processing started: Tue May 13 23:38:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALARM_CLOCK -c ALARM_CLOCK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ALARM_CLOCK -c ALARM_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_CLOCK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_CLOCK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alarm_clock-art " "Info: Found design unit 1: alarm_clock-art" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm_clock " "Info: Found entity 1: alarm_clock" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_CONTROLLER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_CONTROLLER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alarm_controller-art " "Info: Found design unit 1: alarm_controller-art" {  } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm_controller " "Info: Found entity 1: alarm_controller" {  } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DECODER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DECODER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-art " "Info: Found design unit 1: decoder-art" {  } { { "DECODER.vhd" "" { Text "E:/PLDS/CLOCK/DECODER.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "DECODER.vhd" "" { Text "E:/PLDS/CLOCK/DECODER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_COUNTER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_COUNTER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alarm_counter-art " "Info: Found design unit 1: alarm_counter-art" {  } { { "ALARM_COUNTER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_COUNTER.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm_counter " "Info: Found entity 1: alarm_counter" {  } { { "ALARM_COUNTER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_COUNTER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_REG.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_REG.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alarm_reg-art " "Info: Found design unit 1: alarm_reg-art" {  } { { "ALARM_REG.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_REG.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm_reg " "Info: Found entity 1: alarm_reg" {  } { { "ALARM_REG.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_REG.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DISPLAY_DRIVER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DISPLAY_DRIVER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display_driver-art " "Info: Found design unit 1: display_driver-art" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 display_driver " "Info: Found entity 1: display_driver" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FQ_DIVIDER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FQ_DIVIDER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fq_divider-art " "Info: Found design unit 1: fq_divider-art" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/PLDS/CLOCK/FQ_DIVIDER.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fq_divider " "Info: Found entity 1: fq_divider" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/PLDS/CLOCK/FQ_DIVIDER.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "P_ALARM.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file P_ALARM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 p_alarm " "Info: Found design unit 1: p_alarm" {  } { { "P_ALARM.vhd" "" { Text "E:/PLDS/CLOCK/P_ALARM.vhd" 3 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_buffer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_buffer-art " "Info: Found design unit 1: key_buffer-art" {  } { { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 key_buffer " "Info: Found entity 1: key_buffer" {  } { { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led_display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file led_display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led_display-led_display_arch " "Info: Found design unit 1: led_display-led_display_arch" {  } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 led_display " "Info: Found entity 1: led_display" {  } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ALARM_CLOCK " "Info: Elaborating entity \"ALARM_CLOCK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_EXPR_ELEMENT_NUMBER_MISMATCH" "8 7 ALARM_CLOCK.vhd(93) " "Error (10344): VHDL expression error at ALARM_CLOCK.vhd(93): expression has 8 elements, but must have 7 elements" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 93 0 0 } }  } 0 10344 "VHDL expression error at %3!s!: expression has %1!d! elements, but must have %2!d! elements" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue May 13 23:38:59 2008 " "Error: Processing ended: Tue May 13 23:38:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Error: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 2 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}