///////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005-2007 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /   Vendor			: Xilinx// \   \   \/    Version		: $Name: i+IP+131489 $//  \   \        Application		: MIG//  /   /        Filename		: ddr2_32Mx32_data_path_0.v// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $// \   \  /  \   Date Created		: Mon May 2 2005//  \___\/\___\// Device	: Spartan-3/3A/3A-DSP// Design Name	: DDR2 SDRAM// Purpose	: This module has the write and read data paths for the//                DDR2 memory interface. The write data along with write enable//                signals are forwarded to the DDR IOB FFs. The read data is//                captured in CLB FFs and finally input to FIFOs.///////////////////////////////////////////////////////////////////////////////`include "../rtl/ddr2_32Mx32_parameters_0.v"`timescale 1ns/100psmodule ddr2_32Mx32_data_path_0  (   input [((`DATA_WIDTH*2)-1):0]       user_input_data,   input [((`DATA_MASK_WIDTH*2) -1):0] user_data_mask,   input                               clk,   input                               clk90,   input                               reset,   input                               reset90,   input                               write_enable,   input                               rst_dqs_div_in,   input [4:0]                         delay_sel,   input [(`DATA_WIDTH-1):0]           dq,   input [(`DATA_STROBE_WIDTH-1):0]    dqs_int_delay_in,   output                              u_data_val,   output [((`DATA_WIDTH*2)-1):0]      user_output_data,   output                              write_en_val,   output [((`DATA_MASK_WIDTH)-1):0]   data_mask_f,   output [((`DATA_MASK_WIDTH)-1):0]   data_mask_r,   output [(`DATA_WIDTH-1):0]          write_data_falling,   output [(`DATA_WIDTH-1):0]          write_data_rising   );   wire [3:0]                         fifo0_rd_addr;   wire [3:0]                         fifo1_rd_addr;   wire                               read_valid_data_1;   wire  [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr;              wire  [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr;      wire  [(`DATA_STROBE_WIDTH-1):0]   dqs_delayed_col0;   wire  [(`DATA_STROBE_WIDTH-1):0]   dqs_delayed_col1;   wire  [(`DATA_STROBE_WIDTH-1):0]   fifo_0_wr_en/* synthesis syn_keep=1 */;   wire  [(`DATA_STROBE_WIDTH-1):0]   fifo_1_wr_en/* synthesis syn_keep=1 */;   ddr2_32Mx32_data_read_0 data_read0     (      .clk90             (clk90),      .reset90           (reset90),      .ddr_dq_in         (dq),      .read_valid_data_1 (read_valid_data_1),      .fifo_0_wr_en	 (fifo_0_wr_en),      .fifo_1_wr_en	 (fifo_1_wr_en),      .fifo_0_wr_addr    (fifo_0_wr_addr),      .fifo_1_wr_addr    (fifo_1_wr_addr),      .dqs_delayed_col0  (dqs_delayed_col0),      .dqs_delayed_col1  (dqs_delayed_col1),      .user_output_data  (user_output_data),      .fifo0_rd_addr_val (fifo0_rd_addr),      .fifo1_rd_addr_val (fifo1_rd_addr )      );   ddr2_32Mx32_data_read_controller_0  data_read_controller0     (      .clk                   (clk),      .clk90                 (clk90),      .reset                 (reset),       .reset90               (reset90),      .rst_dqs_div_in        (rst_dqs_div_in),      .delay_sel             (delay_sel),      .dqs_int_delay_in      (dqs_int_delay_in),      .fifo_0_wr_en_val      (fifo_0_wr_en),      .fifo_1_wr_en_val      (fifo_1_wr_en),      .fifo_0_wr_addr_val    (fifo_0_wr_addr),      .fifo_1_wr_addr_val    (fifo_1_wr_addr),      .dqs_delayed_col0_val  (dqs_delayed_col0),      .dqs_delayed_col1_val  (dqs_delayed_col1),      .fifo0_rd_addr         (fifo0_rd_addr),      .fifo1_rd_addr         (fifo1_rd_addr),      .u_data_val            (u_data_val),      .read_valid_data_1_val (read_valid_data_1)      );   ddr2_32Mx32_data_write_0 data_write0     (      .user_input_data    (user_input_data),      .user_data_mask     (user_data_mask),      .clk90              (clk90),      .write_enable       (write_enable),      .write_en_val       (write_en_val),      .write_data_falling (write_data_falling),      .write_data_rising  (write_data_rising),      .data_mask_f        (data_mask_f),      .data_mask_r        (data_mask_r)      );endmodule