?? ddr2_32mx32_data_read_controller_0.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: i+IP+131489 $
// \ \ Application : MIG
// / / Filename : ddr2_32Mx32_data_read_controller_0.v
// /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:18 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3A/3A-DSP
// Design Name : DDR2 SDRAM
// Purpose : This module has instantiations fifo_0_wr_en, fifo_1_wr_en,
// dqs_delay and wr_gray_cntr.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"
module ddr2_32Mx32_data_read_controller_0
(
input clk,
input clk90,
input reset,
input reset90,
input rst_dqs_div_in,
input [4:0] delay_sel,
input [3:0] fifo0_rd_addr,
input [3:0] fifo1_rd_addr,
input [(`DATA_STROBE_WIDTH-1):0] dqs_int_delay_in,
output [(`DATA_STROBE_WIDTH-1):0] fifo_0_wr_en_val,
output [(`DATA_STROBE_WIDTH-1):0] fifo_1_wr_en_val,
output [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr_val,
output [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr_val,
output [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0_val,
output [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1_val,
output u_data_val,
output read_valid_data_1_val
);
reg read_valid_data_r;
reg read_valid_data_r1;
reg [3:0] fifo_0_wr_addr_d;
reg [3:0] fifo_0_wr_addr_2d;
reg [3:0] fifo_0_wr_addr_3d;
reg [3:0] fifo_1_wr_addr_d;
reg [3:0] fifo_1_wr_addr_2d;
reg [3:0] fifo_1_wr_addr_3d;
reg u_data_val_r;
reg reset90_r;
reg reset_r;
wire fifo_0_empty;
wire fifo_1_empty;
wire read_valid_data_0_1;
wire rst_dqs_div;
wire [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr;
wire [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr;
wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0;
wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1;
wire [(`DATA_STROBE_WIDTH-1):0] rst_dqs_delay_n;
wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0_n;
wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1_n;
wire [(`DATA_STROBE_WIDTH-1):0] fifo_0_wr_en/* synthesis syn_keep=1 */;
wire [(`DATA_STROBE_WIDTH-1):0] fifo_1_wr_en/* synthesis syn_keep=1 */;
assign fifo_0_wr_addr_val = fifo_0_wr_addr;
assign fifo_1_wr_addr_val = fifo_1_wr_addr;
assign fifo_0_wr_en_val = fifo_0_wr_en;
assign fifo_1_wr_en_val = fifo_1_wr_en;
assign dqs_delayed_col0_val = dqs_delayed_col0;
assign dqs_delayed_col1_val = dqs_delayed_col1;
assign dqs_delayed_col0_n = ~ dqs_delayed_col0;
assign dqs_delayed_col1_n = ~ dqs_delayed_col1;
assign read_valid_data_0_1 = ((~fifo_0_empty) & (~fifo_1_empty));
assign read_valid_data_1_val = (read_valid_data_0_1);
assign u_data_val = u_data_val_r;
assign fifo_0_empty = (fifo0_rd_addr == fifo_0_wr_addr_3d)
? 1'b1 : 1'b0;
assign fifo_1_empty = (fifo1_rd_addr == fifo_1_wr_addr_3d)
? 1'b1 : 1'b0;
always @(posedge clk)
reset_r <= reset;
always @(posedge clk90)
reset90_r <= reset90;
always @(posedge clk90) begin
if(reset90_r)begin
fifo_0_wr_addr_d <= 4'h0;
fifo_1_wr_addr_d <= 4'h0;
fifo_0_wr_addr_2d <= 4'h0;
fifo_1_wr_addr_2d <= 4'h0;
fifo_0_wr_addr_3d <= 4'h0;
fifo_1_wr_addr_3d <= 4'h0;
end
else begin
fifo_0_wr_addr_d <= fifo_0_wr_addr[3:0];
fifo_1_wr_addr_d <= fifo_1_wr_addr[3:0];
fifo_0_wr_addr_2d <= fifo_0_wr_addr_d;
fifo_1_wr_addr_2d <= fifo_1_wr_addr_d;
fifo_0_wr_addr_3d <= fifo_0_wr_addr_2d;
fifo_1_wr_addr_3d <= fifo_1_wr_addr_2d;
end
end
always @(posedge clk90) begin
if(reset90_r) begin
u_data_val_r <= 1'b0;
read_valid_data_r <= 1'b0;
read_valid_data_r1 <= 1'b0;
end
else begin
read_valid_data_r <= read_valid_data_0_1;
read_valid_data_r1 <= read_valid_data_r;
u_data_val_r <= read_valid_data_r1;
end
end
// rst_dqs_div instantation.
ddr2_32Mx32_dqs_delay rst_dqs_div_delayed1
(
.clk_in(rst_dqs_div_in),
.sel_in(delay_sel),
.clk_out(rst_dqs_div)
);
//DQS Internal Delay Circuit implemented in LUTs
genvar dly_i;
generate
for(dly_i = 0; dly_i < `DATA_STROBE_WIDTH; dly_i = dly_i + 1)
begin: gen_delay
ddr2_32Mx32_dqs_delay dqs_delay_col0
(
.clk_in (dqs_int_delay_in[dly_i]),
.sel_in (delay_sel),
.clk_out (dqs_delayed_col0[dly_i])
)/* synthesis syn_preserve=1 */;
ddr2_32Mx32_dqs_delay dqs_delay_col1
(
.clk_in (dqs_int_delay_in[dly_i]),
.sel_in (delay_sel),
.clk_out (dqs_delayed_col1[dly_i])
)/* synthesis syn_preserve=1 */;
end
endgenerate
// FIFO write enables instances
genvar wren_i;
generate
for(wren_i = 0; wren_i < `DATA_STROBE_WIDTH; wren_i = wren_i + 1)
begin: gen_wr_en
ddr2_32Mx32_fifo_0_wr_en_0 fifo_0_wr_en_inst
(
.clk (dqs_delayed_col1_n [wren_i]),
.reset (reset_r),
.din (rst_dqs_div),
.rst_dqs_delay_n (rst_dqs_delay_n[wren_i]),
.dout (fifo_0_wr_en[wren_i])
);
ddr2_32Mx32_fifo_1_wr_en_0 fifo_1_wr_en_inst
(
.clk (dqs_delayed_col0[wren_i]),
.rst_dqs_delay_n (rst_dqs_delay_n[wren_i]),
.reset (reset_r),
.din (rst_dqs_div),
.dout (fifo_1_wr_en[wren_i])
);
end
endgenerate
//FIFO write pointer instances
genvar wr_addr_i;
generate
for(wr_addr_i = 0; wr_addr_i < `DATA_STROBE_WIDTH; wr_addr_i = wr_addr_i + 1)
begin: gen_wr_addr
ddr2_32Mx32_wr_gray_cntr fifo_0_wr_addr_inst
(
.clk (dqs_delayed_col1[wr_addr_i]),
.reset (reset_r),
.cnt_en (fifo_0_wr_en[wr_addr_i]),
.wgc_gcnt (fifo_0_wr_addr[wr_addr_i*4+:4])
);
ddr2_32Mx32_wr_gray_cntr fifo_1_wr_addr_inst
(
.clk (dqs_delayed_col0_n[wr_addr_i]),
.reset (reset_r),
.cnt_en (fifo_1_wr_en[wr_addr_i]),
.wgc_gcnt (fifo_1_wr_addr[wr_addr_i*4+:4])
);
end
endgenerate
endmodule
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