///////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005-2007 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /   Vendor			: Xilinx// \   \   \/    Version		: $Name: i+IP+131489 $//  \   \        Application		: MIG//  /   /        Filename		: ddr2_32Mx32_s3_dq_iob.v// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $// \   \  /  \   Date Created		: Mon May 2 2005//  \___\/\___\// Device	: Spartan-3/3A/3A-DSP// Design Name	: DDR2 SDRAM// Purpose	:///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100psmodule ddr2_32Mx32_s3_dq_iob  (   inout  ddr_dq_inout,   input  write_data_falling,   input  write_data_rising,   input  clk90,   input  write_en_val,   output read_data_in   );   localparam GND = 1'b0;   localparam CLOCK_EN = 1'b1;   wire ddr_en;       wire ddr_dq_q;     wire enable_b;   wire write_data_rising1;   wire write_data_falling1;   assign enable_b = ~ write_en_val;// # delays are used for simulation purpose(delta delay).   assign #1 write_data_rising1  = write_data_rising;   assign #1 write_data_falling1 = write_data_falling;//Transmission data path   FDDRRSE DDR_OUT     (      .Q  (ddr_dq_q),      .C0 (~clk90),      .C1 (clk90),      .CE (CLOCK_EN),      .D0 (write_data_rising1),      .D1 (write_data_falling1),      .R  (GND),      .S  (GND)      );  (* IOB = "TRUE" *) FD DQ_T     (      .D   (enable_b),      .C   (~clk90),      .Q   (ddr_en)      )/* synthesis syn_useioff = 1 */;   OBUFT DQ_OBUFT     (      .I (ddr_dq_q),      .T (ddr_en),      .O (ddr_dq_inout)      );//Receive data path   IBUF DQ_IBUF     (      .I (ddr_dq_inout),      .O (read_data_in)      );endmodule