///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005-2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor			: Xilinx
// \   \   \/    Version		: $Name: i+IP+131489 $
//  \   \        Application		: MIG
//  /   /        Filename		: ddr2_32Mx32_data_path_iobs_0.v
// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:17 $
// \   \  /  \   Date Created		: Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the instantiations s3_dq_iob, s3_dqs_iob 
//		  and ddr_dm modules.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps
`include "../rtl/ddr2_32Mx32_parameters_0.v"

module ddr2_32Mx32_data_path_iobs_0
  (
   input                             clk,
   input                             clk90,
   input                             dqs_reset,
   input                             dqs_enable,
   inout  [(`DATA_STROBE_WIDTH-1):0] ddr_dqs,
   inout  [(`DATA_WIDTH-1):0]        ddr_dq,
   inout  [(`DATA_STROBE_WIDTH-1):0] ddr_dqs_n,
   output [(`DATA_STROBE_WIDTH-1):0] dqs_int_delay_in,
   output [((`DATA_MASK_WIDTH)-1):0]  ddr_dm,
   input  [(`DATA_WIDTH-1):0]        write_data_falling,
   input  [(`DATA_WIDTH-1):0]        write_data_rising,
   input                             write_en_val,
   input  [(`DATA_MASK_WIDTH-1):0]   data_mask_f,
   input  [(`DATA_MASK_WIDTH-1):0]   data_mask_r,
   output [(`DATA_WIDTH-1):0]        ddr_dq_val
   );

   wire [(`DATA_WIDTH-1):0] 	     ddr_dq_in;
 
   assign ddr_dq_val = ddr_dq_in;

 genvar mask_i;
     generate
     for(mask_i = 0; mask_i < `DATA_MASK_WIDTH; mask_i = mask_i+1) begin: gen_dm
       ddr2_32Mx32_s3_dm_iob_0 s3_dm_iob_inst
      (
      .ddr_dm       (ddr_dm[mask_i]),
      .mask_falling (data_mask_f[mask_i]),
      .mask_rising  (data_mask_r[mask_i]),
      .clk90        (clk90)
      );
     end
     endgenerate  


   

//******************************************************************************
// Read Data Capture Module Instantiations
//******************************************************************************
// DQS IOB instantiations
//******************************************************************************

    
  genvar dqs_i;
  generate
    for(dqs_i = 0; dqs_i < `DATA_STROBE_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
         ddr2_32Mx32_s3_dqs_iob  s3_dqs_iob_inst
     (
      .clk            (clk),
      .ddr_dqs_reset  (dqs_reset),
      .ddr_dqs_enable (dqs_enable),
      .ddr_dqs        (ddr_dqs[dqs_i]),
      .ddr_dqs_n      (ddr_dqs_n[dqs_i]),
      .dqs            (dqs_int_delay_in[dqs_i])
	  );
  end
  endgenerate



 
//******************************************************************************
// DDR Data bit instantiations
//******************************************************************************

   genvar dq_i;
   generate
      for(dq_i = 0; dq_i < `DATA_WIDTH; dq_i = dq_i+1) begin: gen_dq
	 ddr2_32Mx32_s3_dq_iob  s3_dq_iob_inst
	   (
	    .ddr_dq_inout       (ddr_dq[dq_i]),
	    .write_data_falling (write_data_falling[dq_i]),
	    .write_data_rising  (write_data_rising[dq_i]),
	    .read_data_in       (ddr_dq_in[dq_i]),
	    .clk90              (clk90),
	    .write_en_val       (write_en_val)
	    );
      end
   endgenerate

endmodule