///////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005-2007 Xilinx, Inc.// This	design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /	/\/   /// /___/  \  /   Vendor			: Xilinx// \   \   \/    Version		: $Name: i+IP+131489 $//  \	\        Application		: MIG//  /   /        Filename		: ddr2_32Mx32_s3_dm_iob_0.v// /___/   /\    Date Last Modified	: $Date: 2007/09/21 15:23:18 $// \   \  /  \   Date Created		: Mon May 2 2005//  \___\/\___\// Device	: Spartan-3/3A/3A-DSP// Design Name	: DDR2 SDRAM// Purpose	: This module has instantiation DDR IOB output flip-flops, //	          and an output buffer for the data mask bits.///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100ps`include "../rtl/ddr2_32Mx32_parameters_0.v"module ddr2_32Mx32_s3_dm_iob_0  (   input   mask_falling,   input   mask_rising,   input   clk90,   output  ddr_dm   );   wire mask_o;     wire gnd;   wire vcc;   assign gnd = 1'b0;   assign vcc = 1'b1;// Data	Mask Output during a write command   FDDRRSE  DDR2_DM0_OUT     (      .Q  (mask_o),      .C0 (~clk90),      .C1 (clk90),      .CE (vcc),      .D0 (mask_rising),      .D1 (mask_falling),      .R  (gnd),      .S  (gnd)      );   OBUF  DM0_OBUF      (       .I (mask_o),       .O (ddr_dm)       );endmodule