# ProjNav -> New Source -> TBW
e:\資料\計算機設(shè)計與實踐\mycpu16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
cpu_16.lso
# xst flow : RunXST
cpu_16.syr
cpu_16.prj
cpu_16.sprj
cpu_16.ana
cpu_16.stx
cpu_16.cmd_log
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
cpu_16_wave.vhw
cpu_16_wave.ano
cpu_16_wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
cpu_16_wave.vhw
cpu_16_wave.ano
cpu_16_wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
cpu_16_wave.vhw
cpu_16_wave.ano
cpu_16_wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
cpu_16_wave.vhw
cpu_16_wave.ano
cpu_16_wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
e:\資料\計算機設(shè)計與實踐\mycpu16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
e:\資料\計算機設(shè)計與實踐\mycpu16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
e:\資料\計算機設(shè)計與實踐\mycpu16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
clock.lso
# xst flow : RunXST
clock.syr
clock.prj
clock.sprj
clock.ana
clock.stx
clock.cmd_log
clock.ngc
clock.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設(shè)計與實踐\mycpu16/_ngo
clock.ngd
clock_ngdbuild.nav
clock.bld
.untf
clock.cmd_log
# Implementation : Map
clock_map.ncd
clock.ngm
clock.pcf
clock.nc1
clock.mrp
clock_map.mrp
clock.mdf
__projnav/map.log
clock.cmd_log
MAP_NO_GUIDE_FILE_CPF "clock"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
clock.twr
clock.twx
clock.tsi
clock.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
clock.ncd
clock.par
clock.pad
clock_pad.txt
clock_pad.csv
clock.pad_txt
clock.dly
reportgen.log
clock.xpi
clock.grf
clock.itr
clock_last_par.ncd
__projnav/par.log
clock.placed_ncd_tracker
clock.routed_ncd_tracker
clock.cmd_log
PAR_NO_GUIDE_FILE_CPF "clock"
# Generate Programming File
__projnav/clock_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
clock.ut
# Generate Programming File
clock.bgn
clock.rbt
clock.ll
clock.msk
clock.drc
clock.nky
clock.bit
clock.bin
clock.isc
clock.cmd_log
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
cw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
cw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
alu.lso
# xst flow : RunXST
alu.syr
alu.prj
alu.sprj
alu.ana
alu.stx
alu.cmd_log
alu.ngc
alu.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設(shè)計與實踐\mycpu16/_ngo
alu.ngd
alu_ngdbuild.nav
alu.bld
.untf
alu.cmd_log
# Implementation : Map
alu_map.ncd
alu.ngm
alu.pcf
alu.nc1
alu.mrp
alu_map.mrp
alu.mdf
__projnav/map.log
alu.cmd_log
MAP_NO_GUIDE_FILE_CPF "alu"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
alu.twr
alu.twx
alu.tsi
alu.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
alu.ncd
alu.par
alu.pad
alu_pad.txt
alu_pad.csv
alu.pad_txt
alu.dly
reportgen.log
alu.xpi
alu.grf
alu.itr
alu_last_par.ncd
__projnav/par.log
alu.placed_ncd_tracker
alu.routed_ncd_tracker
alu.cmd_log
PAR_NO_GUIDE_FILE_CPF "alu"
# Generate Programming File
__projnav/alu_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
alu.ut
# Generate Programming File
alu.bgn
alu.rbt
alu.ll
alu.msk
alu.drc
alu.nky
alu.bit
alu.bin
alu.isc
alu.cmd_log
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設(shè)計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
code.lso
# xst flow : RunXST
code.syr
code.prj
code.sprj
code.ana
code.stx
code.cmd_log
code.ngc
code.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設(shè)計與實踐\mycpu16/_ngo
code.ngd
code_ngdbuild.nav
code.bld
.untf
code.cmd_log
# Implementation : Map
code_map.ncd
code.ngm
code.pcf
code.nc1
code.mrp
code_map.mrp
code.mdf
__projnav/map.log
code.cmd_log
MAP_NO_GUIDE_FILE_CPF "code"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
code.twr
code.twx
code.tsi
code.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
code.ncd
code.par
code.pad
code_pad.txt
code_pad.csv
code.pad_txt
code.dly
reportgen.log
code.xpi
code.grf
code.itr
code_last_par.ncd
__projnav/par.log
code.placed_ncd_tracker
code.routed_ncd_tracker
code.cmd_log
PAR_NO_GUIDE_FILE_CPF "code"
# Generate Programming File
__projnav/code_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
code.ut
# Generate Programming File
code.bgn
code.rbt
code.ll
code.msk
code.drc
code.nky
code.bit
code.bin
code.isc
code.cmd_log
# XST (Creating Lso File) : 
memory.lso
# xst flow : RunXST
memory.syr
memory.prj
memory.sprj
memory.ana
memory.stx
memory.cmd_log
memory.ngc
memory.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設(shè)計與實踐\mycpu16/_ngo
memory.ngd
memory_ngdbuild.nav
memory.bld
.untf
memory.cmd_log
# Implementation : Map
memory_map.ncd
memory.ngm
memory.pcf
memory.nc1
memory.mrp
memory_map.mrp
memory.mdf
__projnav/map.log
memory.cmd_log
MAP_NO_GUIDE_FILE_CPF "memory"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
memory.twr
memory.twx
memory.tsi
memory.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
memory.ncd
memory.par
memory.pad
memory_pad.txt
memory_pad.csv
memory.pad_txt
memory.dly
reportgen.log
memory.xpi
memory.grf
memory.itr
memory_last_par.ncd
__projnav/par.log
memory.placed_ncd_tracker
memory.routed_ncd_tracker
memory.cmd_log
PAR_NO_GUIDE_FILE_CPF "memory"
# Generate Programming File
__projnav/memory_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
memory.ut
# Generate Programming File
memory.bgn
memory.rbt
memory.ll
memory.msk
memory.drc
memory.nky
memory.bit
memory.bin
memory.isc
memory.cmd_log
# XST (Creating Lso File) : 
visit_memory.lso
# xst flow : RunXST
visit_memory.syr
visit_memory.prj
visit_memory.sprj
visit_memory.ana
visit_memory.stx
visit_memory.cmd_log
visit_memory.ngc
visit_memory.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設(shè)計與實踐\mycpu16/_ngo
visit_memory.ngd
visit_memory_ngdbuild.nav
visit_memory.bld
.untf
visit_memory.cmd_log
# Implementation : Map
visit_memory_map.ncd
visit_memory.ngm
visit_memory.pcf
visit_memory.nc1
visit_memory.mrp
visit_memory_map.mrp
visit_memory.mdf