?? mycpu16.gfl
字號:
__projnav/map.log
visit_memory.cmd_log
MAP_NO_GUIDE_FILE_CPF "visit_memory"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
visit_memory.twr
visit_memory.twx
visit_memory.tsi
visit_memory.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
visit_memory.ncd
visit_memory.par
visit_memory.pad
visit_memory_pad.txt
visit_memory_pad.csv
visit_memory.pad_txt
visit_memory.dly
reportgen.log
visit_memory.xpi
visit_memory.grf
visit_memory.itr
visit_memory_last_par.ncd
__projnav/par.log
visit_memory.placed_ncd_tracker
visit_memory.routed_ncd_tracker
visit_memory.cmd_log
PAR_NO_GUIDE_FILE_CPF "visit_memory"
# Generate Programming File
__projnav/visit_memory_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
visit_memory.ut
# Generate Programming File
visit_memory.bgn
visit_memory.rbt
visit_memory.ll
visit_memory.msk
visit_memory.drc
visit_memory.nky
visit_memory.bit
visit_memory.bin
visit_memory.isc
visit_memory.cmd_log
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) :
alu.lso
# xst flow : RunXST
alu.syr
alu.prj
alu.sprj
alu.ana
alu.stx
alu.cmd_log
alu.ngc
alu.ngr
# XST (Creating Lso File) :
code.lso
# xst flow : RunXST
code.syr
code.prj
code.sprj
code.ana
code.stx
code.cmd_log
code.ngc
code.ngr
# XST (Creating Lso File) :
memory.lso
# xst flow : RunXST
memory.syr
memory.prj
memory.sprj
memory.ana
memory.stx
memory.cmd_log
memory.ngc
memory.ngr
# XST (Creating Lso File) :
visit_memory.lso
# xst flow : RunXST
visit_memory.syr
visit_memory.prj
visit_memory.sprj
visit_memory.ana
visit_memory.stx
visit_memory.cmd_log
visit_memory.ngc
visit_memory.ngr
# XST (Creating Lso File) :
write_back.lso
# xst flow : RunXST
write_back.syr
write_back.prj
write_back.sprj
write_back.ana
write_back.stx
write_back.cmd_log
write_back.ngc
write_back.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\資料\計算機設計與實踐\mycpu16/_ngo
write_back.ngd
write_back_ngdbuild.nav
write_back.bld
.untf
write_back.cmd_log
# Implementation : Map
write_back_map.ncd
write_back.ngm
write_back.pcf
write_back.nc1
write_back.mrp
write_back_map.mrp
write_back.mdf
__projnav/map.log
write_back.cmd_log
MAP_NO_GUIDE_FILE_CPF "write_back"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
write_back.twr
write_back.twx
write_back.tsi
write_back.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
write_back.ncd
write_back.par
write_back.pad
write_back_pad.txt
write_back_pad.csv
write_back.pad_txt
write_back.dly
reportgen.log
write_back.xpi
write_back.grf
write_back.itr
write_back_last_par.ncd
__projnav/par.log
write_back.placed_ncd_tracker
write_back.routed_ncd_tracker
write_back.cmd_log
PAR_NO_GUIDE_FILE_CPF "write_back"
# XST (Creating Lso File) :
cpu_16.lso
# xst flow : RunXST
cpu_16.syr
cpu_16.prj
cpu_16.sprj
cpu_16.ana
cpu_16.stx
cpu_16.cmd_log
alu.ngc
clock.ngc
code.ngc
memory.ngc
visit_memory.ngc
write_back.ngc
cpu_16.ngc
alu.ngr
clock.ngr
code.ngr
memory.ngr
visit_memory.ngr
write_back.ngr
cpu_16.ngr
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) :
cpu_16.lso
# xst flow : RunXST
cpu_16.syr
cpu_16.prj
cpu_16.sprj
cpu_16.ana
cpu_16.stx
cpu_16.cmd_log
alu.ngc
clock.ngc
code.ngc
memory.ngc
visit_memory.ngc
write_back.ngc
cpu_16.ngc
alu.ngr
clock.ngr
code.ngr
memory.ngr
visit_memory.ngr
write_back.ngr
cpu_16.ngr
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\資料\計算機設計與實踐\MyCPU16\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
ALU_WAVE.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
ALU_WAVE.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
cw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
code_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
memory_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
visit_memory_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
ALU_WAVE.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
cpu_16_wave.vhw
cpu_16_wave.ano
cpu_16_wave.tfw
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
cpu_16_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
ALU_WAVE.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
cw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
code_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
memory_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
visit_memory_wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
wave.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
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