-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

-- DATE "04/17/2008 10:23:17"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	alu IS
    PORT (
	OP : IN std_logic_vector(3 DOWNTO 0);
	clk : IN std_logic;
	reset : IN std_logic;
	write : IN std_logic;
	dinput : IN std_logic_vector(15 DOWNTO 0);
	sel : IN std_logic;
	C : OUT std_logic;
	Z : OUT std_logic;
	result : OUT std_logic_vector(15 DOWNTO 0)
	);
END alu;

ARCHITECTURE structure OF alu IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_OP : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_write : std_logic;
SIGNAL ww_dinput : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_sel : std_logic;
SIGNAL ww_C : std_logic;
SIGNAL ww_Z : std_logic;
SIGNAL ww_result : std_logic_vector(15 DOWNTO 0);
SIGNAL clk_acombout : std_logic;
SIGNAL OP_a3_a_acombout : std_logic;
SIGNAL OP_a2_a_acombout : std_logic;
SIGNAL reduce_or_a11 : std_logic;
SIGNAL OP_a1_a_acombout : std_logic;
SIGNAL dinput_a12_a_acombout : std_logic;
SIGNAL OP_a0_a_acombout : std_logic;
SIGNAL write_acombout : std_logic;
SIGNAL reset_acombout : std_logic;
SIGNAL sel_acombout : std_logic;
SIGNAL B_a0_a_a109 : std_logic;
SIGNAL B_a12_a : std_logic;
SIGNAL A_a0_a_a134 : std_logic;
SIGNAL A_a12_a : std_logic;
SIGNAL dinput_a7_a_acombout : std_logic;
SIGNAL B_a7_a : std_logic;
SIGNAL A_a7_a : std_logic;
SIGNAL dinput_a2_a_acombout : std_logic;
SIGNAL B_a2_a : std_logic;
SIGNAL A_a2_a : std_logic;
SIGNAL dinput_a1_a_acombout : std_logic;
SIGNAL B_a1_a : std_logic;
SIGNAL A_a1_a : std_logic;
SIGNAL dinput_a0_a_acombout : std_logic;
SIGNAL B_a0_a : std_logic;
SIGNAL add_a1666 : std_logic;
SIGNAL add_a1672 : std_logic;
SIGNAL add_a1677 : std_logic;
SIGNAL add_a1924 : std_logic;
SIGNAL add_a1678 : std_logic;
SIGNAL Mux_a3077 : std_logic;
SIGNAL A_a0_a : std_logic;
SIGNAL add_a1668 : std_logic;
SIGNAL add_a1668COUT1_1941 : std_logic;
SIGNAL add_a1685 : std_logic;
SIGNAL add_a1685COUT1_1942 : std_logic;
SIGNAL add_a1710 : std_logic;
SIGNAL dinput_a6_a_acombout : std_logic;
SIGNAL B_a6_a : std_logic;
SIGNAL A_a6_a : std_logic;
SIGNAL dinput_a5_a_acombout : std_logic;
SIGNAL B_a5_a : std_logic;
SIGNAL A_a5_a : std_logic;
SIGNAL dinput_a4_a_acombout : std_logic;
SIGNAL B_a4_a : std_logic;
SIGNAL A_a4_a : std_logic;
SIGNAL dinput_a3_a_acombout : std_logic;
SIGNAL B_a3_a : std_logic;
SIGNAL A_a3_a : std_logic;
SIGNAL add_a1715 : std_logic;
SIGNAL add_a1715COUT1_1943 : std_logic;
SIGNAL add_a1740 : std_logic;
SIGNAL add_a1740COUT1_1944 : std_logic;
SIGNAL add_a1745 : std_logic;
SIGNAL add_a1745COUT1_1945 : std_logic;
SIGNAL add_a1770 : std_logic;
SIGNAL add_a1770COUT1_1946 : std_logic;
SIGNAL add_a1775 : std_logic;
SIGNAL dinput_a11_a_acombout : std_logic;
SIGNAL B_a11_a : std_logic;
SIGNAL A_a11_a : std_logic;
SIGNAL dinput_a10_a_acombout : std_logic;
SIGNAL B_a10_a : std_logic;
SIGNAL A_a10_a : std_logic;
SIGNAL dinput_a9_a_acombout : std_logic;
SIGNAL B_a9_a : std_logic;
SIGNAL A_a9_a : std_logic;
SIGNAL dinput_a8_a_acombout : std_logic;
SIGNAL B_a8_a : std_logic;
SIGNAL A_a8_a : std_logic;
SIGNAL add_a1800 : std_logic;
SIGNAL add_a1800COUT1_1947 : std_logic;
SIGNAL add_a1805 : std_logic;
SIGNAL add_a1805COUT1_1948 : std_logic;
SIGNAL add_a1830 : std_logic;
SIGNAL add_a1830COUT1_1949 : std_logic;
SIGNAL add_a1835 : std_logic;
SIGNAL add_a1835COUT1_1950 : std_logic;
SIGNAL add_a1860 : std_logic;
SIGNAL dinput_a15_a_acombout : std_logic;
SIGNAL A_a15_a : std_logic;
SIGNAL B_a15_a : std_logic;
SIGNAL dinput_a14_a_acombout : std_logic;
SIGNAL B_a14_a : std_logic;
SIGNAL A_a14_a : std_logic;
SIGNAL dinput_a13_a_acombout : std_logic;
SIGNAL B_a13_a : std_logic;
SIGNAL A_a13_a : std_logic;
SIGNAL add_a1865 : std_logic;
SIGNAL add_a1865COUT1_1951 : std_logic;
SIGNAL add_a1890 : std_logic;
SIGNAL add_a1890COUT1_1952 : std_logic;
SIGNAL add_a1900 : std_logic;
SIGNAL add_a1900COUT1_1953 : std_logic;
SIGNAL add_a1908 : std_logic;
SIGNAL Mux_a3165 : std_logic;
SIGNAL add_a1936 : std_logic;
SIGNAL add_a1931 : std_logic;
SIGNAL add_a1926 : std_logic;
SIGNAL add_a1925 : std_logic;
SIGNAL add_a1680 : std_logic;
SIGNAL add_a1680COUT1_1967 : std_logic;
SIGNAL add_a1695 : std_logic;
SIGNAL add_a1695COUT1_1968 : std_logic;
SIGNAL add_a1705 : std_logic;
SIGNAL add_a1930 : std_logic;
SIGNAL add_a1929 : std_logic;
SIGNAL add_a1928 : std_logic;
SIGNAL add_a1927 : std_logic;
SIGNAL add_a1725 : std_logic;
SIGNAL add_a1725COUT1_1969 : std_logic;
SIGNAL add_a1735 : std_logic;
SIGNAL add_a1735COUT1_1970 : std_logic;
SIGNAL add_a1755 : std_logic;
SIGNAL add_a1755COUT1_1971 : std_logic;
SIGNAL add_a1765 : std_logic;
SIGNAL add_a1765COUT1_1972 : std_logic;
SIGNAL add_a1785 : std_logic;
SIGNAL add_a1935 : std_logic;
SIGNAL add_a1934 : std_logic;
SIGNAL add_a1933 : std_logic;
SIGNAL add_a1932 : std_logic;
SIGNAL add_a1795 : std_logic;
SIGNAL add_a1795COUT1_1973 : std_logic;
SIGNAL add_a1815 : std_logic;
SIGNAL add_a1815COUT1_1974 : std_logic;
SIGNAL add_a1825 : std_logic;
SIGNAL add_a1825COUT1_1975 : std_logic;
SIGNAL add_a1845 : std_logic;
SIGNAL add_a1845COUT1_1976 : std_logic;
SIGNAL add_a1855 : std_logic;
SIGNAL add_a1939 : std_logic;
SIGNAL add_a1938 : std_logic;
SIGNAL add_a1937 : std_logic;
SIGNAL add_a1875 : std_logic;
SIGNAL add_a1875COUT1_1977 : std_logic;
SIGNAL add_a1885 : std_logic;
SIGNAL add_a1885COUT1_1978 : std_logic;
SIGNAL add_a1905 : std_logic;
SIGNAL add_a1905COUT1_1979 : std_logic;
SIGNAL add_a1919 : std_logic;
SIGNAL add_a1674 : std_logic;
SIGNAL add_a1674COUT1_1954 : std_logic;
SIGNAL add_a1690 : std_logic;
SIGNAL add_a1690COUT1_1955 : std_logic;
SIGNAL add_a1700 : std_logic;
SIGNAL add_a1720 : std_logic;
SIGNAL add_a1720COUT1_1956 : std_logic;
SIGNAL add_a1730 : std_logic;
SIGNAL add_a1730COUT1_1957 : std_logic;
SIGNAL add_a1750 : std_logic;
SIGNAL add_a1750COUT1_1958 : std_logic;
SIGNAL add_a1760 : std_logic;
SIGNAL add_a1760COUT1_1959 : std_logic;
SIGNAL add_a1780 : std_logic;
SIGNAL add_a1790 : std_logic;
SIGNAL add_a1790COUT1_1960 : std_logic;
SIGNAL add_a1810 : std_logic;
SIGNAL add_a1810COUT1_1961 : std_logic;
SIGNAL add_a1820 : std_logic;
SIGNAL add_a1820COUT1_1962 : std_logic;
SIGNAL add_a1840 : std_logic;
SIGNAL add_a1840COUT1_1963 : std_logic;
SIGNAL add_a1850 : std_logic;
SIGNAL add_a1870 : std_logic;
SIGNAL add_a1870COUT1_1964 : std_logic;
SIGNAL add_a1880 : std_logic;
SIGNAL add_a1880COUT1_1965 : std_logic;
SIGNAL add_a1895 : std_logic;
SIGNAL add_a1895COUT1_1966 : std_logic;
SIGNAL add_a1913 : std_logic;
SIGNAL add_a1918 : std_logic;
SIGNAL Mux_a3166 : std_logic;
SIGNAL Mux_a3167 : std_logic;
SIGNAL result_t_a16_a : std_logic;
SIGNAL z1_tmp_a27 : std_logic;
SIGNAL c_tmp : std_logic;
SIGNAL reduce_or_a1 : std_logic;
SIGNAL C_areg0 : std_logic;
SIGNAL result_t_a1_a_a778 : std_logic;
SIGNAL result_t_a2_a_a774 : std_logic;
SIGNAL Mux_a3100 : std_logic;
SIGNAL add_a1738 : std_logic;
SIGNAL result_t_a2_a_a775 : std_logic;
SIGNAL Mux_a3095 : std_logic;
SIGNAL Mux_a3096 : std_logic;
SIGNAL add_a1728 : std_logic;
SIGNAL Mux_a3086 : std_logic;
SIGNAL Mux_a3097 : std_logic;
SIGNAL result_t_a2_a_a776 : std_logic;
SIGNAL result_t_a2_a_a777 : std_logic;
SIGNAL add_a1733 : std_logic;
SIGNAL Mux_a3098 : std_logic;
SIGNAL Mux_a3099 : std_logic;
SIGNAL result_t_a4_a : std_logic;
SIGNAL add_a1743 : std_logic;
SIGNAL result_t_a1_a_a771 : std_logic;
SIGNAL result_t_a1_a_a773 : std_logic;
SIGNAL add_a1748 : std_logic;
SIGNAL add_a1753 : std_logic;
SIGNAL Mux_a3103 : std_logic;
SIGNAL Mux_a3104 : std_logic;
SIGNAL result_t_a1_a_a772 : std_logic;
SIGNAL Mux_a3102 : std_logic;
SIGNAL Mux_a3105 : std_logic;
SIGNAL result_t_a5_a : std_logic;
SIGNAL Mux_a3112 : std_logic;
SIGNAL add_a1783 : std_logic;
SIGNAL Mux_a3113 : std_logic;
SIGNAL add_a1778 : std_logic;
SIGNAL Mux_a3114 : std_logic;
SIGNAL add_a1773 : std_logic;
SIGNAL Mux_a3115 : std_logic;
SIGNAL result_t_a7_a : std_logic;
SIGNAL Mux_a3108 : std_logic;
SIGNAL Mux_a3107 : std_logic;
SIGNAL add_a1758 : std_logic;
SIGNAL Mux_a3109 : std_logic;
SIGNAL add_a1763 : std_logic;
SIGNAL Mux_a3173 : std_logic;
SIGNAL Mux_a3174 : std_logic;
SIGNAL Mux_a3110 : std_logic;
SIGNAL add_a1768 : std_logic;
SIGNAL result_t_a6_a : std_logic;
SIGNAL Z_a155 : std_logic;
SIGNAL add_a1803 : std_logic;
SIGNAL Mux_a3124 : std_logic;
SIGNAL add_a1808 : std_logic;
SIGNAL add_a1813 : std_logic;
SIGNAL Mux_a3125 : std_logic;
SIGNAL Mux_a3126 : std_logic;
SIGNAL Mux_a3127 : std_logic;
SIGNAL result_t_a9_a : std_logic;
SIGNAL add_a1798 : std_logic;
SIGNAL Mux_a3122 : std_logic;
SIGNAL Mux_a3117 : std_logic;
SIGNAL Mux_a3118 : std_logic;
SIGNAL add_a1788 : std_logic;
SIGNAL Mux_a3119 : std_logic;
SIGNAL add_a1793 : std_logic;
SIGNAL Mux_a3120 : std_logic;
SIGNAL Mux_a3121 : std_logic;
SIGNAL result_t_a8_a : std_logic;
SIGNAL add_a1828 : std_logic;
SIGNAL add_a1823 : std_logic;
SIGNAL Mux_a3129 : std_logic;
SIGNAL add_a1818 : std_logic;
SIGNAL Mux_a3130 : std_logic;
SIGNAL Mux_a3131 : std_logic;
SIGNAL Mux_a3171 : std_logic;
SIGNAL Mux_a3172 : std_logic;
SIGNAL Mux_a3132 : std_logic;
SIGNAL result_t_a10_a : std_logic;
SIGNAL add_a1843 : std_logic;
SIGNAL Mux_a3135 : std_logic;
SIGNAL add_a1838 : std_logic;
SIGNAL Mux_a3136 : std_logic;
SIGNAL add_a1833 : std_logic;
SIGNAL Mux_a3137 : std_logic;
SIGNAL Mux_a3134 : std_logic;
SIGNAL result_t_a11_a : std_logic;
SIGNAL Z_a156 : std_logic;
SIGNAL add_a1671 : std_logic;
SIGNAL Mux_a3074 : std_logic;
SIGNAL Mux_a3075 : std_logic;
SIGNAL Mux_a3076 : std_logic;
SIGNAL Mux_a3177 : std_logic;
SIGNAL Mux_a3178 : std_logic;
SIGNAL result_t_a0_a : std_logic;
SIGNAL add_a1703 : std_logic;
SIGNAL Mux_a3085 : std_logic;
SIGNAL add_a1698 : std_logic;
SIGNAL Mux_a3084 : std_logic;
SIGNAL Mux_a3087 : std_logic;
SIGNAL Mux_a3175 : std_logic;
SIGNAL Mux_a3176 : std_logic;
SIGNAL Mux_a3088 : std_logic;
SIGNAL add_a1708 : std_logic;
SIGNAL result_t_a2_a : std_logic;
SIGNAL Mux_a3090 : std_logic;
SIGNAL add_a1713 : std_logic;
SIGNAL add_a1723 : std_logic;
SIGNAL Mux_a3091 : std_logic;
SIGNAL add_a1718 : std_logic;
SIGNAL Mux_a3092 : std_logic;
SIGNAL Mux_a3093 : std_logic;
SIGNAL result_t_a3_a : std_logic;
SIGNAL add_a1683 : std_logic;
SIGNAL add_a1688 : std_logic;
SIGNAL add_a1693 : std_logic;
SIGNAL Mux_a3080 : std_logic;
SIGNAL Mux_a3081 : std_logic;
SIGNAL Mux_a3079 : std_logic;
SIGNAL Mux_a3082 : std_logic;
SIGNAL result_t_a1_a : std_logic;
SIGNAL Z_a154 : std_logic;
SIGNAL add_a1853 : std_logic;
SIGNAL Mux_a3139 : std_logic;
SIGNAL Mux_a3140 : std_logic;
SIGNAL add_a1848 : std_logic;
SIGNAL Mux_a3141 : std_logic;
SIGNAL Mux_a3142 : std_logic;
SIGNAL Mux_a3143 : std_logic;
SIGNAL add_a1858 : std_logic;
SIGNAL Mux_a3144 : std_logic;
SIGNAL result_t_a12_a : std_logic;
SIGNAL add_a1888 : std_logic;
SIGNAL Mux_a3151 : std_logic;
SIGNAL add_a1878 : std_logic;
SIGNAL Mux_a3152 : std_logic;
SIGNAL Mux_a3153 : std_logic;
SIGNAL add_a1883 : std_logic;
SIGNAL Mux_a3169 : std_logic;
SIGNAL Mux_a3170 : std_logic;
SIGNAL Mux_a3154 : std_logic;
SIGNAL result_t_a14_a : std_logic;
SIGNAL add_a1898 : std_logic;
SIGNAL Mux_a3161 : std_logic;
SIGNAL Mux_a3162 : std_logic;
SIGNAL add_a1903 : std_logic;
SIGNAL add_a1893 : std_logic;
SIGNAL Mux_a3158 : std_logic;
SIGNAL Mux_a3159 : std_logic;
SIGNAL Mux_a3157 : std_logic;
SIGNAL Mux_a3160 : std_logic;
SIGNAL Mux_a3156 : std_logic;
SIGNAL result_t_a15_a : std_logic;
SIGNAL add_a1863 : std_logic;
SIGNAL Mux_a3146 : std_logic;
SIGNAL add_a1873 : std_logic;
SIGNAL Mux_a3147 : std_logic;
SIGNAL add_a1868 : std_logic;
SIGNAL Mux_a3148 : std_logic;
SIGNAL Mux_a3149 : std_logic;
SIGNAL result_t_a13_a : std_logic;
SIGNAL Z_a157 : std_logic;
SIGNAL Z_a158 : std_logic;
SIGNAL z1_tmp_a28 : std_logic;
SIGNAL z1_tmp : std_logic;
SIGNAL Z_areg0 : std_logic;
SIGNAL ALT_INV_reset_acombout : std_logic;
SIGNAL ALT_INV_write_acombout : std_logic;

BEGIN

ww_OP <= OP;
ww_clk <= clk;
ww_reset <= reset;
ww_write <= write;
ww_dinput <= dinput;
ww_sel <= sel;
C <= ww_C;
Z <= ww_Z;
result <= ww_result;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
ALT_INV_reset_acombout <= NOT reset_acombout;
ALT_INV_write_acombout <= NOT write_acombout;

clk_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => clk_acombout);

OP_a3_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(3),
	combout => OP_a3_a_acombout);