?? alu.vho
字號:
B_a1_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1925 = !OP_a0_a_acombout & (B[1])
-- B_a1_a = DFFEAS(add_a1925, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a1_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "5050",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => OP_a0_a_acombout,
datac => dinput_a1_a_acombout,
aclr => GND,
sload => VCC,
ena => B_a0_a_a109,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1925,
regout => B_a1_a);
A_a1_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3079 = B_a1_a & (A[1] & (!OP_a1_a_acombout) # !A[1] & OP_a0_a_acombout) # !B_a1_a & (OP_a0_a_acombout & (A[1]) # !OP_a0_a_acombout & OP_a1_a_acombout)
-- A_a1_a = DFFEAS(Mux_a3079, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a1_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "3AE4",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => OP_a0_a_acombout,
datab => OP_a1_a_acombout,
datac => dinput_a1_a_acombout,
datad => B_a1_a,
aclr => GND,
sload => VCC,
ena => A_a0_a_a134,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => Mux_a3079,
regout => A_a1_a);
dinput_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_dinput(0),
combout => dinput_a0_a_acombout);
B_a0_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1924 = OP_a0_a_acombout # B[0]
-- B_a0_a = DFFEAS(add_a1924, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a0_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "FAFA",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => OP_a0_a_acombout,
datac => dinput_a0_a_acombout,
aclr => GND,
sload => VCC,
ena => B_a0_a_a109,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1924,
regout => B_a0_a);
add_a1666_I : cyclone_lcell
-- Equation(s):
-- add_a1666 = A_a0_a $ B_a0_a
-- add_a1668 = CARRY(A_a0_a # !B_a0_a)
-- add_a1668COUT1_1941 = CARRY(A_a0_a # !B_a0_a)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "66BB",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => A_a0_a,
datab => B_a0_a,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1666,
cout0 => add_a1668,
cout1 => add_a1668COUT1_1941);
add_a1672_I : cyclone_lcell
-- Equation(s):
-- add_a1672 = !A_a0_a
-- add_a1674 = CARRY(A_a0_a)
-- add_a1674COUT1_1954 = CARRY(A_a0_a)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "55AA",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => A_a0_a,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1672,
cout0 => add_a1674,
cout1 => add_a1674COUT1_1954);
add_a1677_I : cyclone_lcell
-- Equation(s):
-- add_a1677 = OP_a0_a_acombout & (add_a1672) # !OP_a0_a_acombout & add_a1666
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "EE44",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => OP_a0_a_acombout,
datab => add_a1666,
datad => add_a1672,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1677);
add_a1678_I : cyclone_lcell
-- Equation(s):
-- add_a1678 = A_a0_a $ add_a1924
-- add_a1680 = CARRY(A_a0_a & add_a1924)
-- add_a1680COUT1_1967 = CARRY(A_a0_a & add_a1924)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "6688",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => A_a0_a,
datab => add_a1924,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1678,
cout0 => add_a1680,
cout1 => add_a1680COUT1_1967);
Mux_a3077_I : cyclone_lcell
-- Equation(s):
-- Mux_a3077 = OP_a1_a_acombout & (add_a1677 # OP_a2_a_acombout) # !OP_a1_a_acombout & (!OP_a2_a_acombout & add_a1678)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "datac",
lut_mask => "ADA8",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => OP_a1_a_acombout,
datab => add_a1677,
datac => OP_a2_a_acombout,
datad => add_a1678,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => Mux_a3077);
A_a0_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3177 = B_a0_a & (A[0] & (!Mux_a3077) # !A[0] & OP_a0_a_acombout) # !B_a0_a & (OP_a0_a_acombout & (A[0]) # !OP_a0_a_acombout & Mux_a3077)
-- A_a0_a = DFFEAS(Mux_a3177, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a0_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "3AE4",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => OP_a0_a_acombout,
datab => Mux_a3077,
datac => dinput_a0_a_acombout,
datad => B_a0_a,
aclr => GND,
sload => VCC,
ena => A_a0_a_a134,
devclrn => ww_devclrn,
combout => Mux_a3177,
regout => A_a0_a);
add_a1683_I : cyclone_lcell
-- Equation(s):
-- add_a1683 = B_a1_a $ A_a1_a $ !add_a1668
-- add_a1685 = CARRY(B_a1_a & (!add_a1668 # !A_a1_a) # !B_a1_a & !A_a1_a & !add_a1668)
-- add_a1685COUT1_1942 = CARRY(B_a1_a & (!add_a1668COUT1_1941 # !A_a1_a) # !B_a1_a & !A_a1_a & !add_a1668COUT1_1941)
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "cin",
lut_mask => "692B",
cin0_used => "true",
cin1_used => "true",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => B_a1_a,
datab => A_a1_a,
cin0 => add_a1668,
cin1 => add_a1668COUT1_1941,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1683,
cout0 => add_a1685,
cout1 => add_a1685COUT1_1942);
add_a1708_I : cyclone_lcell
-- Equation(s):
-- add_a1708 = B_a2_a $ A_a2_a $ add_a1685
-- add_a1710 = CARRY(B_a2_a & A_a2_a & !add_a1685COUT1_1942 # !B_a2_a & (A_a2_a # !add_a1685COUT1_1942))
-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
synch_mode => "off",
register_cascade_mode => "off",
sum_lutc_input => "cin",
lut_mask => "964D",
cin0_used => "true",
cin1_used => "true",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => B_a2_a,
datab => A_a2_a,
cin0 => add_a1685,
cin1 => add_a1685COUT1_1942,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1708,
cout => add_a1710);
dinput_a6_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_dinput(6),
combout => dinput_a6_a_acombout);
B_a6_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1930 = B[6] & !OP_a0_a_acombout
-- B_a6_a = DFFEAS(add_a1930, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a6_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "00F0",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
datac => dinput_a6_a_acombout,
datad => OP_a0_a_acombout,
aclr => GND,
sload => VCC,
ena => B_a0_a_a109,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1930,
regout => B_a6_a);
A_a6_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3108 = OP_a2_a_acombout & !B_a6_a & (A[6] # !OP_a0_a_acombout)
-- A_a6_a = DFFEAS(Mux_a3108, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a6_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "00A2",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => OP_a2_a_acombout,
datab => OP_a0_a_acombout,
datac => dinput_a6_a_acombout,
datad => B_a6_a,
aclr => GND,
sload => VCC,
ena => A_a0_a_a134,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => Mux_a3108,
regout => A_a6_a);
dinput_a5_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
oe_power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => ww_devclrn,
devpor => ww_devpor,
devoe => ww_devoe,
oe => GND,
padio => ww_dinput(5),
combout => dinput_a5_a_acombout);
B_a5_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1929 = B[5] & !OP_a0_a_acombout
-- B_a5_a = DFFEAS(add_a1929, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a5_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "00F0",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
datac => dinput_a5_a_acombout,
datad => OP_a0_a_acombout,
aclr => GND,
sload => VCC,
ena => B_a0_a_a109,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => add_a1929,
regout => B_a5_a);
A_a5_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3102 = B_a5_a & (A[5] & !OP_a1_a_acombout # !A[5] & (OP_a0_a_acombout)) # !B_a5_a & (OP_a0_a_acombout & (A[5]) # !OP_a0_a_acombout & OP_a1_a_acombout)
-- A_a5_a = DFFEAS(Mux_a3102, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a5_a_acombout, , , VCC)
-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
synch_mode => "on",
register_cascade_mode => "off",
sum_lutc_input => "qfbk",
lut_mask => "7A64",
output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
clk => clk_acombout,
dataa => B_a5_a,
datab => OP_a1_a_acombout,
datac => dinput_a5_a_acombout,
datad => OP_a0_a_acombout,
aclr => GND,
sload => VCC,
ena => A_a0_a_a134,
devclrn => ww_devclrn,
devpor => ww_devpor,
combout => Mux_a3102,
regout => A_a5_a);
dinput_a4_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
input_register_mode => "none",
output_register_mode => "none",
oe_register_mode => "none",
input_async_reset => "none",
output_async_reset => "none",
oe_async_reset => "none",
input_sync_reset => "none",
output_sync_reset => "none",
oe_sync_reset => "none",
input_power_up => "low",
output_power_up => "low",
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