?? alu.vho

?? 實現16種運算的alu,包括+,-,+1,-1,與或非以及移位比較運算。經調試成功。
?? VHO
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-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a9_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1933,
	regout => B_a9_a);

A_a9_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3124 = B_a9_a & (A[9] & !OP_a1_a_acombout # !A[9] & (OP_a0_a_acombout)) # !B_a9_a & (OP_a0_a_acombout & (A[9]) # !OP_a0_a_acombout & OP_a1_a_acombout)
-- A_a9_a = DFFEAS(Mux_a3124, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a9_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "5CE2",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a1_a_acombout,
	datab => OP_a0_a_acombout,
	datac => dinput_a9_a_acombout,
	datad => B_a9_a,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3124,
	regout => A_a9_a);

dinput_a8_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(8),
	combout => dinput_a8_a_acombout);

B_a8_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1932 = B[8] & !OP_a0_a_acombout
-- B_a8_a = DFFEAS(add_a1932, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a8_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a8_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1932,
	regout => B_a8_a);

A_a8_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3118 = OP_a2_a_acombout & !B_a8_a & (A[8] # !OP_a0_a_acombout)
-- A_a8_a = DFFEAS(Mux_a3118, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a8_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "2022",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a2_a_acombout,
	datab => B_a8_a,
	datac => dinput_a8_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3118,
	regout => A_a8_a);

add_a1798_I : cyclone_lcell
-- Equation(s):
-- add_a1798 = B_a8_a $ A_a8_a $ add_a1775
-- add_a1800 = CARRY(B_a8_a & A_a8_a & !add_a1775 # !B_a8_a & (A_a8_a # !add_a1775))
-- add_a1800COUT1_1947 = CARRY(B_a8_a & A_a8_a & !add_a1775 # !B_a8_a & (A_a8_a # !add_a1775))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "964D",
	cin_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => B_a8_a,
	datab => A_a8_a,
	cin => add_a1775,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1798,
	cout0 => add_a1800,
	cout1 => add_a1800COUT1_1947);

add_a1803_I : cyclone_lcell
-- Equation(s):
-- add_a1803 = A_a9_a $ B_a9_a $ !(!add_a1775 & add_a1800) # (add_a1775 & add_a1800COUT1_1947)
-- add_a1805 = CARRY(A_a9_a & B_a9_a & !add_a1800 # !A_a9_a & (B_a9_a # !add_a1800))
-- add_a1805COUT1_1948 = CARRY(A_a9_a & B_a9_a & !add_a1800COUT1_1947 # !A_a9_a & (B_a9_a # !add_a1800COUT1_1947))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "694D",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => A_a9_a,
	datab => B_a9_a,
	cin => add_a1775,
	cin0 => add_a1800,
	cin1 => add_a1800COUT1_1947,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1803,
	cout0 => add_a1805,
	cout1 => add_a1805COUT1_1948);

add_a1828_I : cyclone_lcell
-- Equation(s):
-- add_a1828 = B_a10_a $ A_a10_a $ (!add_a1775 & add_a1805) # (add_a1775 & add_a1805COUT1_1948)
-- add_a1830 = CARRY(B_a10_a & A_a10_a & !add_a1805 # !B_a10_a & (A_a10_a # !add_a1805))
-- add_a1830COUT1_1949 = CARRY(B_a10_a & A_a10_a & !add_a1805COUT1_1948 # !B_a10_a & (A_a10_a # !add_a1805COUT1_1948))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "964D",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => B_a10_a,
	datab => A_a10_a,
	cin => add_a1775,
	cin0 => add_a1805,
	cin1 => add_a1805COUT1_1948,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1828,
	cout0 => add_a1830,
	cout1 => add_a1830COUT1_1949);

add_a1833_I : cyclone_lcell
-- Equation(s):
-- add_a1833 = B_a11_a $ A_a11_a $ !(!add_a1775 & add_a1830) # (add_a1775 & add_a1830COUT1_1949)
-- add_a1835 = CARRY(B_a11_a & (!add_a1830 # !A_a11_a) # !B_a11_a & !A_a11_a & !add_a1830)
-- add_a1835COUT1_1950 = CARRY(B_a11_a & (!add_a1830COUT1_1949 # !A_a11_a) # !B_a11_a & !A_a11_a & !add_a1830COUT1_1949)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "692B",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => B_a11_a,
	datab => A_a11_a,
	cin => add_a1775,
	cin0 => add_a1830,
	cin1 => add_a1830COUT1_1949,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1833,
	cout0 => add_a1835,
	cout1 => add_a1835COUT1_1950);

add_a1858_I : cyclone_lcell
-- Equation(s):
-- add_a1858 = B_a12_a $ A_a12_a $ (!add_a1775 & add_a1835) # (add_a1775 & add_a1835COUT1_1950)
-- add_a1860 = CARRY(B_a12_a & A_a12_a & !add_a1835COUT1_1950 # !B_a12_a & (A_a12_a # !add_a1835COUT1_1950))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "964D",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => B_a12_a,
	datab => A_a12_a,
	cin => add_a1775,
	cin0 => add_a1835,
	cin1 => add_a1835COUT1_1950,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1858,
	cout => add_a1860);

dinput_a15_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(15),
	combout => dinput_a15_a_acombout);

A_a15_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3074 = OP_a0_a_acombout & (B_a0_a # !OP_a1_a_acombout) # !OP_a0_a_acombout & OP_a1_a_acombout & A[15]
-- A_a15_a = DFFEAS(Mux_a3074, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a15_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "EA62",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a0_a_acombout,
	datab => OP_a1_a_acombout,
	datac => dinput_a15_a_acombout,
	datad => B_a0_a,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3074,
	regout => A_a15_a);

B_a15_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1939 = B[15] & !OP_a0_a_acombout
-- B_a15_a = DFFEAS(add_a1939, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a15_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a15_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1939,
	regout => B_a15_a);

dinput_a14_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(14),
	combout => dinput_a14_a_acombout);

B_a14_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1938 = B[14] & !OP_a0_a_acombout
-- B_a14_a = DFFEAS(add_a1938, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a14_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	datac => dinput_a14_a_acombout,
	datad => OP_a0_a_acombout,
	aclr => GND,
	sload => VCC,
	ena => B_a0_a_a109,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1938,
	regout => B_a14_a);

A_a14_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a3152 = OP_a2_a_acombout & !B_a14_a & (A[14] # !OP_a0_a_acombout)
-- A_a14_a = DFFEAS(Mux_a3152, GLOBAL(clk_acombout), VCC, , A_a0_a_a134, dinput_a14_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00C4",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a0_a_acombout,
	datab => OP_a2_a_acombout,
	datac => dinput_a14_a_acombout,
	datad => B_a14_a,
	aclr => GND,
	sload => VCC,
	ena => A_a0_a_a134,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a3152,
	regout => A_a14_a);

dinput_a13_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_dinput(13),
	combout => dinput_a13_a_acombout);

B_a13_a_aI : cyclone_lcell
-- Equation(s):
-- add_a1937 = B[13] & !OP_a0_a_acombout
-- B_a13_a = DFFEAS(add_a1937, GLOBAL(clk_acombout), VCC, , B_a0_a_a109, dinput_a13_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "00F0",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
上一頁 1 2 3 45
?? 文件大小 403 K
?? 上傳用戶 jl315
?? 所屬分類 VHDL/FPGA/Verilog
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?? alu.vho

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