JDF G
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PROJECT sum
DESIGN sum
DEVFAM virtex
DEVFAMTIME 0
DEVICE xcv200
DEVICETIME 0
DEVPKG pq240
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE sum.vhdl
SOURCE msi.vhdl
SOURCE cu.vhd
SOURCE clock.vhdl
SOURCE ieu.vhdl
STIMULUS pp.tbw
STIMULUS ss.tbw
DEPASSOC sum sum.ucf
[Normal]
xilxBitgStart_Clk=xstvhd, virtex, VHDL.t_bitFile, 1195378597, JTAG Clock
xilxSynthAddBufg=xstvhd, virtex, Schematic.t_synthesize, 1090294626, 0
[STATUS-ALL]
clock.ncdFile=WARNINGS,1195634623
clock.ngdFile=WARNINGS,1195634620
[STRATEGY-LIST]
Normal=True